# double-edged clock in VHDL

#### mahmood.n

##### Member level 5
Using Quartus 12, I would like to know why
Code:
wait until ((clk'event and clk ='1') or (clk'event and clk ='0'));
won't synthesize to a double edge (raise and fall) flip flop? I get this error

Code:
Error (10628): VHDL error at test3.vhd(9): can't implement register for two clock edges combined with a binary operator
Error (10658): VHDL Operator error at test3.vhd(9): failed to evaluate call to operator ""or""
Also, when I wrote
Code:
wait on clk;
in active-hdl the functional simulation shows a double edge flip flop as below

but quartus shows the following error

Code:
Error (10533): VHDL Wait Statement error at test3.vhd(10): Wait Statement must contain condition clause with UNTIL keyword
I know that is related to synthesis templates that tools use. I would like to know which one is closer to standard.

#### FvM

##### Super Moderator
Because you can only synthesize circuit descriptions that are supported by the target hardware. No modern FPGA supports double clock edges.

You can find emulation circuits for double edge clocking in literature comprised of two single edge FFs and additional combinational logic, but they have bad performance and problems in timing closure.

#### mahmood.n

##### Member level 5
So, do you mean the error is device specific?
Or it is a syntax error?

#### FvM

##### Super Moderator
You may call it a device specific problem. But a very general problem if you don't find any logic device that has double edge sensitive FFs. As you found out, it's possible in simulator, hence no VHDL syntax or semantic problem.

However, legal VHDL isn't necessarily synthesizable.

mahmood.n

### mahmood.n

points: 2

#### TrickyDicky

Quartus is giving you its limitations. It requires that you use wait until for synthesiable templates. Its not a syntax error.

While "wait until" can be used for synthesis, its not really very widely used. This would be the normally used (and understood) register template:

Code VHDL - [expand]1
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process(clk)
begin
if rising_ege(clk) then
-- synchronous code
end if;
end process;

mahmood.n

### mahmood.n

points: 2

#### KlausST

##### Super Moderator
Hi,

And often double edge triggered is not useful at all.
What´s your exact application that needs double edge triggering?
...and then: how is timing specified?

***
One of a few double edge applications I know is the DDR interface. But for this the FPGAs often have dedicated hardware periferals.

Klaus

#### FvM

##### Super Moderator
DDR logic doesn't use dual-edge triggered FFs but separate FFs triggered by rising and falling edge.

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