syedshan
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Dear all,
My inner module's output port is 14 bit and outer module's output port is 64 bits.
Hence I connect
But what I am receiving is all ports connected to ground. I am checking this using RTL viewer in ISE
Does VHDL does not support this thing.
I have tried similar thing in verilog and it works perfect.
Please note that for input port similar case works fine in VHDL
Bests,
Shan
My inner module's output port is 14 bit and outer module's output port is 64 bits.
Hence I connect
Code:
In_mod => out_mod(13 downto 0);
while
out_mod(63 downto 14) <= (others => '0');
But what I am receiving is all ports connected to ground. I am checking this using RTL viewer in ISE
Does VHDL does not support this thing.
I have tried similar thing in verilog and it works perfect.
Please note that for input port similar case works fine in VHDL
Bests,
Shan