# Does VHDL does not support different size ports connection(for output)

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#### syedshan

Dear all,

My inner module's output port is 14 bit and outer module's output port is 64 bits.

Hence I connect

Code:
In_mod => out_mod(13 downto 0);

while

out_mod(63 downto 14) <= (others => '0');

But what I am receiving is all ports connected to ground. I am checking this using RTL viewer in ISE

Does VHDL does not support this thing.
I have tried similar thing in verilog and it works perfect.
Please note that for input port similar case works fine in VHDL

Bests,
Shan

#### TrickyDicky

can you post the whole code - your code is not very clear.

#### syedshan

can you post the whole code - your code is not very clear.

I will send you the ports connection part I think. I have just posted the relevant part for your convenience.
Hope this will help.

Code:
entity main_blk is
port(

...
out_0_out_data : out std_logic_vector( 63 downto 0);
...
);
end entity;

architecture behave of main_blk is

component Mean_subt is
generic(
Din_width 	: 	integer	:= 14;
Dout_width	: 	integer	:= 14
);
port (
clk, rst			: in 	std_logic;
EN				: in 	std_logic;
ext_trigger		: in	std_logic;
in_adc			: in 	std_logic_vector(Din_width-1 downto 0);
actual_out		: out std_logic_vector(Dout_width-1 downto 0);
valid_out 		: out std_logic
);
end component;

begin

inst1_mean : Mean_subt
generic map (
Din_width 	=> 14,
Dout_width	=>	14)

port map(
...
...
actual_out		=>	out_0_out_data((13 downto 0),
);

out_0_out_data(63 downto 14) => (others => '0');

end architecture behave;

Bests,
Shan

Last edited:

#### TrickyDicky

There are a couple of issues with the posted code:

actual_out from inst1_mean is 64 bits wide, and you're trying to connect it to a 14 bit bus.
then out_0_out_data has all bits connected to '0', so you would get multiple driver errors (ie. it wont even compile) on out_0_out_data.

So I dont think you posted the code correctly.

#### syedshan

There are a couple of issues with the posted code:

actual_out from inst1_mean is 64 bits wide, and you're trying to connect it to a 14 bit bus.
then out_0_out_data has all bits connected to '0', so you would get multiple driver errors (ie. it wont even compile) on out_0_out_data.

So I dont think you posted the code correctly.
I am really sorry for that.
I have edited the code in my previous message as you mentioned. Now it is as in my actual code

Thank you,
Shan