Does the transistor act as common gate in the schematic?

[Osawa_Odessa]

I want to analyse the circuit below. It is an RF power amplifier.
In DC mode:
Assuming that Ld is ideal then there is no DC voltage drop across it. => VD2 = VDD.
In the mean time, the capacitor is open at DC => no current flowing through Rb => VG2 = VD2 = VDD
In AC mode:
This is where I am confused. It is said that M2 acts as common gate here. This means that the gate of M2, G2, have to be connected to ground in AC mode, right?
But how can that be possible when there is the presence of Cb and Ls?
The voltage at gate of M2, VG2, will be equal to the total voltage across Cb and Ls. But VG2 is impossible zero, right?
And if so how M2 can be a common gate stage? Please explain? Thanks.

 

[kabeer02]

In the case of Ld you shouldn't expect any voltage drop what is their is an inductor M2 is always ready to conduct because of Rb but you can only get the amplified signal when M1 start conducting ...

 

[Osawa_Odessa]

Hi, sorry but I don't understand your point. Could you explain it more?

Ld is an inductor. Assuming that it is ideal then at DC mode, there is no voltage drop across the inductor. Can you explain why M2 is still considered as common gate here?

 

[FvM]

This is actually your fifth thread about basically the same cascode amplifier structure (And it have been even more before being gracefully merged by the moderator). Curiously you're starting new threads about questions that have been already answered previously.

https://www.edaboard.com/threads/299077/
https://www.edaboard.com/threads/300031/
https://www.edaboard.com/threads/300598/
https://www.edaboard.com/threads/300798/

As a simple point to consider, the circuit will only under particular premises work as a cascode amplifier with common gate stage. The art of reading requires as a first step to understand how it is meant by the authors of the original paper.

 

[Osawa_Odessa]

OK, I didn't want to create more anymore thread but because my three previous threads get no answers.

 

[FvM]

I see several answers to your questions.

I was able to retrieve the original citation "A 2.4-GHz 0.18-um CMOS Self-Biased Cascode Power Amplifier". The basic problem is that you have cut the "conventional" and "self-biased cascode" schematics from a paper without explaining the discussed circuit purpose and the relation of both derived by the author.

To give a literal answer to your question, M2 isn't operated in a classical common-gate circuit in the self-biased cascode in post #1, but it's still near to common gate. In my view it's pointless to discuss details without referring to the circuit purpose given in the paper.

By the way, what's your motivation to analyze this specific circuit? Are you doing any work related to RF IC design in sub-µm technology, or is it just a misunderstanding?

 

[Osawa_Odessa]

Hi,
Yes, I should have specified about that.
Did you read the paper?
I don't understand why M2 is still near common gate as its voltage swing sinificantly especially when resistive - diode is added.

By the way, what's your motivation to analyze this specific circuit? Are you doing any work related to RF IC design in sub-µm technology, or is it just a misunderstanding?

Yes, I have a school project in which I need to design a power amplifier and the circuit is what was chosen.

 

[FvM]

I found a discussion about the same paper https://www.designers-guide.org/Forum/YaBB.pl?num=1378636848/4

I particularly appreciate this comment

I am not sure what your ultimate goal is but it has been my experience that trying to learn design from IEEE papers is extremely difficult because the authors assume you have certain basic knowledge and often times leave out important design details. If you are trying to learn about design I suggest using textbooks by authors such as Thomas Lee and Behzad Razavi since they start from very basic principles and build up to more complex topics.

 

[FvM]

One objective of he "self biased" cascode is to balance the peak voltage rating between both transistors to allow higher output level with sub-µm (low voltage rating) transistors. Applying an AC voltage to M2 gate is part of this optimization. But M2 is still essentially working in common base topology - source is input and drain is output node.