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In some applications, propagation delay may not be your only determining factor. You'll need to understand, at a higher level than propagation delay, how the overall chip operates. Usually, you want to understand the bounding frequencies of your design. That is, how low and how high of a frequency you could go and still have the chip work.
For example, if you were designing a DMA path, it would be a good idea to understand the characteristics of the data being DMA'd and the DMA controller. In other cases, altering frequencies between two clock domains could cause synchronization problems.
The next thing I would consider is cost.
I could keep rambling on, but I think you get the idea...
the max frequence is decided by the longest delay path
u should meet the follow :
Tco + Tcl_max + Tsu <= T + Tskew
Tco: Register delay from clk to output
Tcl_max: the max combinational logic delay
Tsu: Setup time
Tskew: CLock skew
anjali .. i think its critical path.. and not propagation delay..critical path is the longest path thru the circuit which decides the operational frequency of the circuit.
I guess you're talking about the max freq of a board, not of a chip. For a board, if the clocking scheme is system synchronous, the propagation delay(accurately, flight time) determines the max freq of your board; while if the clocking scheme is source synchronized, by properly routing your board, there's no propagation/flight time difference between your clock/stobe signal and data bus, then the propagation/flight time will have no impact on your sysytem freq.
hope it helps.
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