Does Logic synthesis of a network depend on input switching activity profile ???

[satishgra]

Hello,

I have a strange problem on mind....While doing logic synthesis, how does the input switching activity profile impact the output of a synthesis tool.

Put in another way, can I develop a synthesis tool that would give me the most optimized netlist for a given input pattern such that the power consumption is the best.

Regards,
Satish

 

[rca]

The synthesis tool take "partially" care of the the switching back annotation provided.