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DFM has become critical for designs below 65nm and below. I have worked on 65nm but didnot see specific rules set for DFM. But for 45nm, DFM is very critical and there are checkers which need to be run after the layout is drc clean
It depends as to whether you being a layout designer will clean ur blocks for DFM as well or whether the foundary will take care of it post layout (for 130 nm & above.).But what i have observed is-on 90 nm and below ( 65 nm , 45 nm), the layout designer is asked to clean the DFM as well , in some cases instantiating those devices which have DFM+analog opton enabled so that when you lay out even small blocks and then use them in hierarchical designs, then block automatically becomes dfm clean ( as subblocks that are being used are DFM clean now.)
For 45 nm, mostly the automated tool will create DFM containers which can be instantiated over ur block to achieve DFM.(But before putting these DFM containers we need to fix some "must fix DRC errors" ).After putting these containers we again need to run DRC on our block to clean remaing drc errors . Tool usually takes care that these containers are created in such a way that they wont cause shorts with the underlying metal layers in our block.But if some short comes, it has to be adressed.
Advantage of putting DFM containers in that it can be removed if needed(for increasing visibilty of each layer i.e seeing other underneath connections ) as it wont be in same level of hierarchy.
Couls any body explain what is actually DFM( Design for Manufactureing).
I always feel that these are extra robust rules which is use to give better yield. I dont know how foundry remove these DFM.
In lithography ,the illumination source wave length is 193nm ,but the feture size is 90nm,65nm or 45nm,the phsycical dicrimination limite is 1/2 wavelength,so diffration,and intrference occure,the transfered pattern may be distorted even vanished on the wafer when projecting,so OPC,OAI,and PSM are used to adjust this problem,and these method must obey some rules and in design we must obey and use these rule to make our chips designed more easily and precisely manufactured.
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