does flop consume more power in reset state?

[wy21century]

Hi

I am a digital guy. When I am testing our chip in the lab. I found a weird thing

The chip is just power up, the most up stream block is output constant signal by default. We didn't do any configuration at all.

The weird thing is when I apply a global reset to digital core (hold reset to be always active), I found total power goes up significantly (from 320mW to 399mW)

My question is: does flop consume more power in reset state (clock is always toggling before and after reset)?

Thanks
Ben

 

[HTA]

Hi,

by "flop" you mean a flipflop I guess. If so, I think this could be if it has a static operation. Someone would have to look into the schematics in the data sheet.

Enjoy your design work!

 

[wy21century]

Hi,

by "flop" you mean a flipflop I guess. If so, I think this could be if it has a static operation. Someone would have to look into the schematics in the data sheet.

Enjoy your design work!

Thanks for the reply!

Yes, I meant a flipflop in std cell library from foundry. Is there a common sense that which one (reset, !reset) consume more power?

 

[HTA]

Hi,

There are so many different types of flipflop designs that maybe only the detailed transistor schematic, or the cell designer can give a good reasoning for the difference. So I think no common sense!

Enjoy your design work!

 

[erikl]

... when I apply a global reset to digital core (hold reset to be always active), I found total power goes up significantly (from 320mW to 399mW)

My question is: does flop consume more power in reset state (clock is always toggling before and after reset)?

How do you measure the power: dynamically (i.e. during the active reset edge), static (e.g. during a full clock cycle), the max. during a clock cycle, or a medium value for several clock cycles?

Background: If the reset signal - which probably feeds many reset inputs, often thousands of them - has a fanout violation problem, i.e. the reset buffer (chain) feeds (many) more reset inputs than it is designed for: fanout of reset buffer (chain) « number of reset inputs fed, the reset edges may become very slow, up to in the millisecond range! During about one third of these slow edges (from vthn to vdd-vthp (or the other way round)) - at many reset inputs simultaneously - these reset input gates draw a lot of cross current, because during this time both transistors are ON.

Of course this is just a dynamic problem (even if it could momentarily overcharge your power supply, because this current could get in the order of 1mA per reset input), the power consumption - depending on how you performed the measurement - could well result in such higher value.

 

[dick_freebird]

At short channel lengths there is always significant DC
leakage current and this current is modulated by logic
state (stacks leaking more or less depending on how
many "off" vs "on" gates in series / parallel). Reset is
going to touch a lot of things. One question is, how
much IDDQ variation do you see along the rest of the
truth table? If it's not grossly out of bed then maybe
reset is just one of the "outlier" states in terms of how
leakage is summed.