Hi,
Actually I become confused again.. and may be need more clerification that what exactly you wnated to know..
See if you are talking about FF/SS/FS/SF transistor , then you should know what's the base behind that...
as per my understanding ...
Slow and fast concept depends on the channel length and channel width (or you can say the width and the length of the transistor)... Layout cannot be fabricated exactly as drawn in the layout due to the limitations in the manufacturing process, such as process tolerances and mask misalignment. Some of the manufacturing limitations are captured in the Spice transistor model.
so if I assume DW is the delta difference of drawn W from effective W and DL is the delta difference of drawn L from effective L. Transistor effective channel length can be affected by under-etching or over-etching of the poly, as well as the amount of lateral diffusion under the gate. The effective channel width of the transistor is affected by the “bird peak” of the isolation scheme. In addition, the inclination of the gate poly up to the field oxide makes it difficult to determine the exact width of the transistor.
Considering an example where DL is 0.015um and DW is 0.045um. To simulate a “fast” corner transistor, the transistor is modeled (in the spice netlist) to have a narrower L and a wider W. On the contrary, a “slow” corner transistor is modeled with a wider L and a smaller W. Hence, at the fast corner DL is negative (i.e. -0.015um) and DW is positive while at the slow corner DL is positive and DW is negative (i.e. -0.045um).
Similarly -- there are few more Process variation -- like variation in the doping densities, which also contribute in the fast and Slow type of Transistors. but this type of variation is difficult to model in the Spice simulation.
Due to these variation -- the threshold voltages of NMOS or PMOS changes (there are lot of other variation like temperature varaition- changes the mobility - changes the Vth). So If you are looking for a formula or something as a direct relation ship between Vthp and Vthn with respect to SS/FF/SF/FS transistor, then I am not sure whether that is possible or not. As per my understanding its very difficult to find out a direct relationship between these 2 parameter.
If you want a general relationship-- keeping most of the variation parameter constant, then you can cehck any basic book -- and you can easily derive a formula...
So if you think- that I misunderstood you question and your question was different .. please let me know.
Hope above information helps you.