Does anyone have any idea about how to **** a technology model file?

[dhaval4987]

I need to test process variation effect on timing behavior of a circuit. for that I need to change some parameters of technology model file. I know that some parameters are inter-related and so I need to learn the model hacking procedures.

Does anyone know how to heck a model file?
Or may be- how should I proceed with this problem?

 

[birdy123]

Hi,

I think there is no need to **** any thing. if you are talking about the synopsys nxtgrd file, then its too easy to regenerate it. Just let me know which one are you using .. then it will be easy for me or anyone to help u.

 

[dhaval4987]

thanks birdy.. I am using 45nm PTM model and i need to see its variatioin effects. Now suppose i change Vth (for an example), there are many many parameters in technology model that are affected. So I dont know all of them and their interdependence. Thats why i need to learn haccking. If you know how to do one, then I would really appreciate. I am using 45nm PTM model, and I have no clue what nxtgrd is.

 

[birdy123]

Hi ,
I got your point. Its look like that you are using freely avaliable models.. anyways. Just wanted to know whether you are aware about following site.
Predictive Technology Model (PTM)

in this they have procedure to regenerate the models files. You can change the different paramenter and then you can generate the model files. And is you want to see the changes .. then you can copy those in a txt file and then can do the diff in unix.

I hope this will help you. Let me know if it doesn't work for you or you think I didn't get your point till now.

 

[dhaval4987]

Thank you very much! I must say it helped! Will bother you in future if i get confused or need help...

 

[birdy123]

sure any time.

 

[dhaval4987]

@ Birdy

If I just want to test the circuit behavior at different corners- just a coarse analysis- what and how should i change parameters?

I understand that SS means NMOS and PMOS both slow and FF means both fast... but is there any correlation in between the amount of change of Vth of one with Vth of the other?

I mean, If I increase Vthn, then by what amount should I increase Vthp for SS? how about SF, FS and FF Vice Versa?

 

[birdy123]

Hi,

Actually I become confused again.. and may be need more clerification that what exactly you wnated to know..

See if you are talking about FF/SS/FS/SF transistor , then you should know what's the base behind that...
as per my understanding ...

Slow and fast concept depends on the channel length and channel width (or you can say the width and the length of the transistor)... Layout cannot be fabricated exactly as drawn in the layout due to the limitations in the manufacturing process, such as process tolerances and mask misalignment. Some of the manufacturing limitations are captured in the Spice transistor model.
so if I assume DW is the delta difference of drawn W from effective W and DL is the delta difference of drawn L from effective L. Transistor effective channel length can be affected by under-etching or over-etching of the poly, as well as the amount of lateral diffusion under the gate. The effective channel width of the transistor is affected by the “bird peak” of the isolation scheme. In addition, the inclination of the gate poly up to the field oxide makes it difficult to determine the exact width of the transistor.
Considering an example where DL is 0.015um and DW is 0.045um. To simulate a “fast” corner transistor, the transistor is modeled (in the spice netlist) to have a narrower L and a wider W. On the contrary, a “slow” corner transistor is modeled with a wider L and a smaller W. Hence, at the fast corner DL is negative (i.e. -0.015um) and DW is positive while at the slow corner DL is positive and DW is negative (i.e. -0.045um).

Similarly -- there are few more Process variation -- like variation in the doping densities, which also contribute in the fast and Slow type of Transistors. but this type of variation is difficult to model in the Spice simulation.

Due to these variation -- the threshold voltages of NMOS or PMOS changes (there are lot of other variation like temperature varaition- changes the mobility - changes the Vth). So If you are looking for a formula or something as a direct relation ship between Vthp and Vthn with respect to SS/FF/SF/FS transistor, then I am not sure whether that is possible or not. As per my understanding its very difficult to find out a direct relationship between these 2 parameter.

If you want a general relationship-- keeping most of the variation parameter constant, then you can cehck any basic book -- and you can easily derive a formula...

So if you think- that I misunderstood you question and your question was different .. please let me know.

Hope above information helps you.

 

[dhaval4987]

Thanks for the explaination. I understand about SS/FF etc and why there are variations. I can vary W, Leff, tox etc parameters to observe the effects Similarly I can change Vth and observe the effect.

All I cant realize is that if there is any relation of Vth change in PMOS and NMOS? Say to run it at a slower speed, if I increase Vthn by 0.1V, do I need to increase Vthp by 0.1 only or it could be anyother value and completely independent?

What are the books that focus on this topic rather than the normal circuit design stuff?

 

[birdy123]

Hi,

I am not sure about the relationship between Vthp and vthn.. but as I mentioned that u can cehck the book.

Books you can refer related to CMOS design like
Principles CMOS VLSI Design By Weste
CMOS: Circuit Design, Layout, and Simulation by Jacob.

I think you will find this typr of relationship only in the basic books only.

 

[dhaval4987]

thanks. Weste and Harris has good stuff. And as far as relation between Vths is concerned- i dont see it there. But still- useful one.