I am trying to model TSV in HFSS. I have no idea about TSV sizing in different technologies. Do you know any reference or document including the size of the TSVs in different CMOS technologies(especially 180n and 65n)?
As far as I know TSV is not related to the CMOS technology as they are two different processes. One example of TSVs I have worked with were 50 µm in diameter (non-filled). Wafer thickness was generally <200 µm because of low etch rates. Material was tungsten, about 1 µm thick.