Do you guys really use the function & Procedure in VHDL?

[spriteice]

How many of you actually declare a Function or a Procedure in VHDL?

For me, I only use Procedure for simulation.

Is it feasible to use function/procedure for synthesizable designs?

Maybe it's because I haven't done any functional verifcation design?

 

[maestor]

Re: Do you guys really use the function & Procedure in V

Hi,

I use functions in synthesizable VHDL in every single design.
I don't use procedures in synthesizable VHDL.
I use procedures and functions in behavioural VHDL.

I didn't use to have functions in my RTL... and now I think they are as useful as they can be in other programming languages (C for example).
Everybody here knows the advantages of functions so no discussion about that...

--maestor

 

[bibo1978]

Re: Do you guys really use the function & Procedure in V

Both function and procedure can be synthesizable, the main difference between them is that function returns only one signal but a procedure may return many, I used both function, procedure in behavioral and RTL code. Although the function or the procedure may not be synthesizable but you can use them as well to configure your attributes in a synthesizable code ,I have done that.

thats all folks

 

[paviljonac]

i use vhdl for fpga design. i don't use neither functions nor procedures.

 

[Mazi3]

Re: Do you guys really use the function & Procedure in V

only on special occasions when i have birthday for example

 

[madjid]

Re: Do you guys really use the function & Procedure in V

Hi,
Why not, function and procedure are both synthesizable and are good ways to modular programming.

 

[Mazi3]

Re: Do you guys really use the function & Procedure in V

actualy, i sam, that everybody use their own style of programming. my for example is as i call it "register level". personaly i don't use equality, more or less operators in code but build circuit with subtracter instead

other coder's use quite abstract level in their coding

100 people, 100 codes

 

[Aser]

Re: Do you guys really use the function & Procedure in V

I use functions and procedures for
synthesis some complex paralel logic circuits.
Some considerations are contra to use own procedures and functions:
- it would be better to use functions from standard packages (if any), because
own functions can be synthesized and modeled substantially worse,
- the program with specific functions is usually less readable, and then it is less reusable,
- functions and most of procedures are not used for sequential models...

 

[omara007]

Re: Do you guys really use the function & Procedure in V

functions and procedures are not recommended when u code in RTL level .. even though all of u guys have mentioned that these things are synthesizable .. u forgot to tell that the function for example is synthesized each time it's called !! ..

if you want a good RTL code .. try not to use such things .. u can always avoid .. i myself have deisgned 5 complete processors and never had to use anything of that in my RTL .. at the same time, they can be very useful in verification and testing ..

Just Enjoy my opinion

 

[maestor]

Re: Do you guys really use the function & Procedure in V

Hi omara007,

What do u mean by:

...if you want a good RTL code...try not to use such things...

I don't agree m8. If u r a good hdl engineer and u know what u r doing and how synthesizers respond/infer your RTL then that's it!

Imagine you have to write an AAL5 reassembler (for example) and you have to calculate a crc-32, don't tell me your entity will include the rtl code to do that with all the XOR'ing junk or otherwise it will call a 'calc_crc32' function in your pkg which can also be REUSED by another module (for example the transmiter side of your AAL5 assembler). Ah! and before that you have calculated the HEC of your ATM cell, so again...have u called your 'calc_hec' function or you have written in ur RTL all the XOr'ing stuff.

I am not reinventing the wheel man. There is no point in writting the same rtl in 2 entities if they r doing the same thing, just put it in a package and ur synthesizer won't bother. It's going to replicate the logic if it has to in both cases, with or without functions.

And I'll tell u more... I use RECORDs, omg! k:

And they r one of the most powerful things to use in VHDL in the market I'm working on and using records makes me use functions all over the place.

-maestor

 

[the_penetrator]

Re: Do you guys really use the function & Procedure in V

i agree with you.

VHDL is not a programming language but a hardware description language. Functions and procedures donnot fit really well. I discourage their use in VHDL designs.

On the other hand, passing in/out ports as records is a GREAT idea that most synthesis tools already support. Personally, it has helped in modifying an existing RISC to add some architectural stuff at the control path. It was very easy and clean to add more fields in the decoded instruction word, add a couple of instruction extensions.

I think if this design didn't use records it would be frustrating.

the_penetrator©

 

[omara007]

Re: Do you guys really use the function & Procedure in V

You guys need to read (Reuse Methodology Manual) ..
no more .. no less ..
hope u guys went for the fab before .. not just IPs ..
BTW .. not using functions and procedures in ur RTL doesn't necess. mean u substitute that with gates ..

Just Enjoy

 

[maestor]

Re: Do you guys really use the function & Procedure in V

HI omara007,

I don't know what u mean with...

'you guys need to read (Reuse Methodology Manual)'...

Every module my collegues and myself write here must be reusable and even more, fully configurable and parametrizable (when that is possible)... not only synthetizable and with no functions.

I still can't believe people are not using functions in HDL, HDL describes HW, so what? these r not the old days when synthesizers couldn't figure out what to do...

I've seen fab RTL using functions...

-amestor

 

[omara007]

Re: Do you guys really use the function & Procedure in V

Reuse Methodology Manual is like a Bible to designers ..
anyhow .. this is my point of view guys .. i stated that before .. and I have an experience in that .. so , u can take it .. and sure u can leave it .. it's not physics

Don't be that pissed off

Just Enjoy

 

[maestor]

Re: Do you guys really use the function & Procedure in V

Yep...

let's leave it like that...it's like a Barcelona and a Real Madrid supporter talking about football.

If after all ur experience u still don't use functions... I guess nobody can convince u until u convince yourself.

take care,

-maestor

 

[omara007]

Re: Do you guys really use the function & Procedure in V

let me guys express u my opinion .. am not against function along the road .. but i have fears from it .. and i'll tell u what are those ..

I didn't claim that subprograms are not Synthesizable .. this can't be done cuz simply tools can prove the opposite .. i just claimed that it's NOT the Best RTL For Synthesis .. and this is true from my opinion .. sometimes function do get synthesized more than once .. and this is completely true for some cases .. and rather than that ..

And Although nesting of functions and procedures is allowed also to any level of complexity, and recursion is also supported in VHDL basically, YET of course, if you expect to generate actual hardware from your VHDL descriptions using synthesis tools, then you will need to avoid writing recursive functions and procedures, as such descriptions are not synthesizable .. hence, if not synthesizable, then it's not good RTL ..

MY CLAIM was that .. and am not forcing anyone to believe it's PHYSICS



Again .. just Enjoy

 

[maestor]

Re: Do you guys really use the function & Procedure in V

Hi,

.. sometimes function do get synthesized more than once .. and this is completely true for some cases .. and rather than that ..

in what cases...? :? it could just be that u actually needed that logic twice...just see the example of the calc_crc32, u need to calculate CRC-32 twice, u write the code once in ur package and the Synthesis tool will infer 2 of them...just because u need them. If u want to use calc_crc32 again in 6 months, u just add that package again and don't modify ur RTL...

and recursion is also supported in VHDL basically, YET of course, if you expect to generate actual hardware from your VHDL descriptions using synthesis tools, then you will need to avoid writing recursive functions and procedures, as such descriptions are not synthesizable .. hence, if not synthesizable, then it's not good RTL ..

Recursion is another issue, and... recursion is synthesisable m8. Can you synthesize a 'loop' or not...?

for i in state.event'range loop
if state.event(i) = CONGESTION1 or state.event(i) = CONGESTION2 then
state.cong_detected <= true;
end if;
end loop;

That is synthesizable and is recursive...the only issue is timing, u have to go through the combinational loop in a clk period.

I don't like procedures for Synthesis either, we agree in something then

Regards,
-maestor

 

[omara007]

Re: Do you guys really use the function & Procedure in V

Good we agree
i guess it's some kinda SCHOOLs in design .. and all is about synthesis tools .. one day WAIT was very forbidden .. i remember that day .. i was a student ..
anyhow .. there is nothing like PHYSICs rules here .. u can always do what u want .. but with some goals achieved and some draw-bax .. u can't always win without any trade-offs ..

 

[pyrite]

Re: Do you guys really use the function & Procedure in V

I believe fpga synthesis tools (like quartusII) don't understand function, isn't it?

 

[vomit]

Re: Do you guys really use the function & Procedure in V

functions and procedures are not recommended when u code in RTL level .. even though all of u guys have mentioned that these things are synthesizable .. u forgot to tell that the function for example is synthesized each time it's called !! ..

if you want a good RTL code .. try not to use such things .. u can always avoid .. i myself have deisgned 5 complete processors and never had to use anything of that in my RTL .. at the same time, they can be very useful in verification and testing ..

Just Enjoy my opinion

I too strongly disagree. "synthesized each time it's called" means ONCE, as synthesis isn't simulation. For a function to be synthesizable, it is called with const parameters and returns a const value. This is just the same as putting the function code inline, but much cleaner as it is only needed once.

Another very useful function of functions is the initialisation of lookup tables (which can actually speed up your design):

with a "function initfunc return table_type" you can do

constant c_MyLookupTable : table_type := initfunc;

and have a table initialised with an algorithm instead of tedious error-prone typing.

So if you fear functions, you should really try to lose your feelings and start to appreciate them. The code becomes much more maintainable.

The same goes for procedures. If you e.g. have a state machine with in each state

case state1 =>
   ValidData<='1'
   DataOut<="101010";
   output3<= ... etc
case state2 =>
   ValidData<='1'
   DataOut<="-------";
   output3<= ... etc

then it really makes sense to make a procedure

procedure OutputValidData(d:unsigned);
procedure NoValidData;

and put

case state1 =>
   OutputValidData("101010");
case state2 =>
   NoValidData;

Much more readable, maintainable and less risk for errors if you forget an assignment.