.. sometimes function do get synthesized more than once .. and this is completely true for some cases .. and rather than that ..
and recursion is also supported in VHDL basically, YET of course, if you expect to generate actual hardware from your VHDL descriptions using synthesis tools, then you will need to avoid writing recursive functions and procedures, as such descriptions are not synthesizable .. hence, if not synthesizable, then it's not good RTL ..
omara007 said:functions and procedures are not recommended when u code in RTL level .. even though all of u guys have mentioned that these things are synthesizable .. u forgot to tell that the function for example is synthesized each time it's called !! ..
if you want a good RTL code .. try not to use such things .. u can always avoid .. i myself have deisgned 5 complete processors and never had to use anything of that in my RTL .. at the same time, they can be very useful in verification and testing ..
Just Enjoy my opinion
constant c_MyLookupTable : table_type := initfunc;
case state1 =>
ValidData<='1'
DataOut<="101010";
output3<= ... etc
case state2 =>
ValidData<='1'
DataOut<="-------";
output3<= ... etc
procedure OutputValidData(d:unsigned);
procedure NoValidData;
case state1 =>
OutputValidData("101010");
case state2 =>
NoValidData;
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