isdf verilog
hello all,
Thank you for your responses, Im in the ASIC, the prob is with .v file generated with SNPS DC , I want to simulate the file to check the functionality of the design after being mapped to 180 nm library,
I took the same .v file and simulated in Xilinx , but it is not simulated,
So, where should I simulate this file, It is showing error in Xilinx ...Im unable to verify the .V file, I need to verify this .v file so that i can go for placement and routing
Thanks in Advance
Arun