Do I need synchronization when I transfer data from clk A to B domain or vice version

[omid219]

Hi
I have two busses in my design, let's call them A & B.
The clock for B comes from a divider of clk A.
Do I need any synchronization when I transfer data from clk A to B domain or vice versa?

Thanks,

 

[nand_gates]

Re: synchronization

In your case I dont think you need synchronization.

 

[utmseng]

Re: synchronization

In my opinion, we only do synchronization for the asynchronous signals. Data which are synchronous in clocks need not be synchronized.

 

[bronzefury]

Re: synchronization

You are going to need FIFOs between the two domains, one for A to B and another for B to A.

clock for A and clock for B, although synchronous, have different frequencies and will also have different phases.

 

[omid219]

Re: synchronization

The data is not in burst format, so there is no need to FIFO. I just don't know do I need synchronizers or not.
At the first glance it seems that because clock B is generated by dividing clk A, they are synchronuse and don't need any synchronizer. But it is obvious that clock B is coming a little bit after clock A, because of dividing FF delay. So we may violate the hold time when data is moving from domain A to B. Am I right?

 

[bronzefury]

Re: synchronization

The data is not in burst format, so there is no need to FIFO.

How many clocks per data are there? How frequent is the data updated?

I just don't know do I need synchronizers or not.
At the first glance it seems that because clock B is generated by dividing clk A, they are synchronuse and don't need any synchronizer. But it is obvious that clock B is coming a little bit after clock A, because of dividing FF delay. So we may violate the hold time when data is moving from domain A to B. Am I right?

Note that clock B may not always come "a little bit" after clock A. clock B will most likely have its own clock tree which means there could be more than a divider-flop worth of delay between edges of clock B and clock A.

Also, depending on how the divider flop starts, whether starting at logic 1 or logic 0, clock B could be 180 degrees out-of-phase from what you expect. How do you control the divider flop's starting logic level? (Reset?)

In any case, I think it would be best to design your logic circuit with the assumption that clock B and clock A are out-of-phase from each other with varying degrees.

That being said, assuming data isn't bursty...

For clock domain A to clock domain B, where A is a faster frequency than B, I would be concerned about A data being latched by clock B correctly. So, first thing I would do is make sure data is valid in A long enough for B to capture it. I would also synchronize a data_enable-like signal from A to B because setup and hold times could be violated.

For clock domain B to clock domain A, where B is a slower frequency than A, data from B is already valid for two A clocks. However, you'll still need a synchronized data_enable-like signal from B to A because, just like A to B above, setup and hold times could be violated when data is transferred from B to A.

In either of the two cases, you might need to keep data stable long enough to be captured by the target domain. How long you have to keep data valid depends on your synchronization circuit and how data is captured by the target domain.

How would you constrain this path during synthesis and STA?

 

[eeeraghu]

Re: synchronization

Hi,

Well here it all depends on how many clock pulses the data is flowing, and the frequency of the clock divided, suppose for eample the data is flowing in two clock pulses once and u r using frequency divivder by 2 clock for the B Bus, then its not necessary as the data will be in the phase of the rising edges of the clocks.

And do not consider the delays by the clock while deciding for the synchronizer. And if the data forms a part of burst then its must to use a fifo.

Well if not use a Handshaking mechanism here, it would be appropriate.

Regards
Raghu

 

[sameer_dlh25]

Re: synchronization

Also, depending on how the divider flop starts, whether starting at logic 1 or logic 0, clock B could be 180 degrees out-of-phase from what you expect. How do you control the divider flop's starting logic level? (Reset?)

In any case initial value of divider flop does not matter as long as metastability is concerned.Since CLK A and CLK B edges are always aligned.
But still I feel a handshaking is required, because in some of the cases of burst starting of first data may not be uniform.[/code]

 

[bronzefury]

Re: synchronization

In any case initial value of divider flop does not matter as long as metastability is concerned.Since CLK A and CLK B edges are always aligned.
But still I feel a handshaking is required, because in some of the cases of burst starting of first data may not be uniform.

How is it guaranteed that CLK A and CLK B are aligned? Isn't there a clock tree for both clock domains? Isn't it best to design a circuit independent of clock alignment?

 

[ami]

Re: synchronization

1.CLKB should be generated (divided by 2) from neg-edge of CLKA, so that you can ignore the setup/hold time when synchronization.
2.if you use clock tree for CLKA and CLKB, remember to set constraint on those clock tree, so that CLKA and CLKB can have a balance and fixed phase relationship though out your chip
3.clock skew / transition / max min delay between CLKA and CLKB are depended on the frequency and the size of your chip.
4. Synchronization data between 2 clock domains must be from register

 

[nemolee]

Re: synchronization

CLKA and CLKB are synchronous even if they have a little bit delay caused by DFF. Depends on IC design rule, if the clocks are from the same source or synchronization, they don't need any other process for it.

 

[deva_eda]

synchronization

As far as i know there is not need to synchronize data from a clock and its divided clock as they signals between these clocks obey the setup and hold constraints.

 

[vedamrit]

Re: synchronization

kindly go through the attached document before implementing synchronizers in ur design

 

[alam.tauqueer]

synchronization

In your case I dont think you required any synchronizer.