[SOLVED] Do counters accumulate PLL jitter?

[mabderezai]

Do counters accumulate the jitter from a PLL? Meaning that after counting up to N, the time elapsed is NT +jitter, is it NT + (N*Jitter)^.5?

I am of the thinking that it is NT+jitter, but my boss keeps telling me its the latter. I have tried proving it to him for the past 3 day, but he insist that he is right, and that the accumulated jitter in the counter is a source of noise in our ADC. I am at a point that if I push it any further I might get into trouble at work. So PLEASE help.... I can't imagine a counter would accumulate jitter, even tho if it does I'll accept it, learn why, and move on.

:roll:

 

[crutschow]

I agree with you. A digital counter simply counts transitions of the signal, nothing more. So the total count time would be N times the average time of one count or NT + jitter. Jitter is usually due to random noise and is plus or minus around the average signal period so it's not cumulative, its average is zero. If you look at the frequency of the signal you will see that it remains essentially the same (assuming its a stable signal source) no matter how long you average the count. If the jitter were cumulative, this wouldn't be true.

Ask you boss to explain his reasoning. I'd like to hear that myself. Insisting you are right because you're the boss doesn't cut it. :wink:

 

[ZekeR]

It's a matter of how you define "jitter"...

See here: https://en.wikipedia.org/wiki/Jitter#Jitter_metrics

If you prefer the definition of "absolute jitter," then the measurement time will be NT+jitter. Only the error of the final clock edge matters to your ADC's measurement.

However, if your boss is thinking of "period jitter," then the measurement error will be the probabilistic sum of each clock edge's jitter, and will be sqrt(N*jitter).

The measurement error is obviously constant regardless of which equation you use; you just have to use the appropriate definition for what jitter is. In other words, you could both be right.

Edit:

To clarify on a point... You're right, the counter doesn't accumulate the period jitter; the accumulation occurs in the oscillator.

 

[mabderezai]

It's a matter of how you define "jitter"...
To clarify on a point... You're right, the counter doesn't accumulate the period jitter; the accumulation occurs in the oscillator.

A flip flop is a memoryless system from one edge to the next. The oscillator is not memoryless due to the feedback, and so jitter accumulates in the oscillator, but the net impact of that jitter would then get corrected by the PLL loop, unless the PLL doesn't have the response time to correct for the jitter that would accumulate in a reference clock period, which means that its a bad PLL design and it would cycle slip and the divider would have timing issues and god knows what other things would happen.

Boss is boss, and arguing with any boss would not lead to happy endings, plus not that many mixed signal design jobs in Los Angeles :-?
I don't know how to pretend to be taking account accumulated of PLL jitter in an ADC. Maybe after Thanksgiving my boss would have an epiphany.

Thanks all!

 

[permute]

This assumes the PLL's source is also jitter free, or at least free of low/mid frequency jitter.

The PLL should act as a jitter filter, but will also track low-frequency jitter.