DLL question - duty cycle of input clock is 30%~70%

[gavin168]

DLL question

I am designing a DLL project, working range is 40MHz~240MHz, but the duty cycle of input clock is 30%~70%.

I plan to do:

1), in order to lock correctly, the delay will be forced to below 1 period when initial. so i plan to reset the vcntrl to be VDD?

2), for the the working range, I plan to use self_biasing to make the charge pump?

3), I preferred to use the differential delay cell, but the input clock is single ended clock with bad duty cycle, so plan to use invert chain to be the VCDL, the vcntrl is connected to a regulated buffer to control the delay.

Hope anyone give me some suggestion. and is there anything should be concerned? Thank you.

 

[coolstuff07]

Re: DLL question

Hi,

Input duty cycle is very important for DLL. Use Duty cycle detector circuit at the input.
Dont use inverter chain it will vary across process and temp which may not lock your DLL for all PVT conditions.


Bye.

 

[gavin168]

Re: DLL question

thank you coolstuff07,

but 40MHz~240MHz clock with 30%~70% duty cycle, to get 50% duty cycle for whole range. Is it difficult to make a duty cycle corrector?

 

[gavin168]

Re: DLL question

can anyone give some suggestion for the duty cycle correct?

And, Is it better to use PD or PFD? Thank you.