DLL in the xilinx-spartan2

[wolfheart_2001]

spartan2 xilinx

hi,
i heard that there is DLL circuit built in the spartan 2 architecture used to correct the clock skew, sorry what does that mean? i saw that the dedicated clock pins are connected to global buffer's and also the DLL output connected to a global buffer then to the design, so which clock skew does the DLL eleminate???

 

[pisoiu]

dll spartan 2

The dedicated clock input pin along with its correspondent clock i/o buffer in one thing, and the internal global clock distribution net is another. They can be connected directly or through DLL. If connected directly, different time delays can appear between different clock nets, depending on the loads. The DLL's main purpose (when is connected) is to ensure a low skew clock distribution inside the chip, using the internal clock distribution networks, by monitoring the output clock with a feedback input. Check the Xilinx Spartan2 datasheet, page 20, module 2.

/pisoiu

 

[wu.po]

xilinx dll

what means the dll pin "locded" after reset

 

[Renjith]

the dll will take some time for clock signal syncronization, till that period the "Locked" signal will not be asserted. Once the DCM corrects the duty cycle and phase, the locked signal will be asserted.

 

[power-twq]

yes , DLL can eliminate the skew between pin's input clock and internal

register's input clock. The DLL delay input clock by one whole clock cycle.

because for a clock, its version that delayed by one cycle will be same

as the original clock. DLL use this principle to eliminate skew.

best regards

hi,
i heard that there is DLL circuit built in the spartan 2 architecture used to correct the clock skew, sorry what does that mean? i saw that the dedicated clock pins are connected to global buffer's and also the DLL output connected to a global buffer then to the design, so which clock skew does the DLL eleminate???