trxguy
Newbie level 4
Hello all,
I designed a 30MHz LPF for SWL, the result is quite good, cut-off point at 33MHz, max attenuation more than 50dB, the curve rising up at 200MHz. I soldered all the component on a tiny single layer pcb (20mmx26mm). Total 4 smd capacitors and 3 smd coils.
But I pull it into a small matellic housing, the result is getting bad, attenuation decreased to 20dB, the curve is rising up on 60MHz.
I have tried to isolate the matellic housing from the gnd (outer BNC connection), it returned to normal (att. >50dB).
It would be affected by parasitic capacitance....
My question is
(1) If I isolate the housing from the gnd, does it be affacted by EMI easily? Does it be an odd design?
(2) How much parastic capacitance should be taken in account?
Is there anybody giving me some idea?
mkchan
I designed a 30MHz LPF for SWL, the result is quite good, cut-off point at 33MHz, max attenuation more than 50dB, the curve rising up at 200MHz. I soldered all the component on a tiny single layer pcb (20mmx26mm). Total 4 smd capacitors and 3 smd coils.
But I pull it into a small matellic housing, the result is getting bad, attenuation decreased to 20dB, the curve is rising up on 60MHz.
I have tried to isolate the matellic housing from the gnd (outer BNC connection), it returned to normal (att. >50dB).
It would be affected by parasitic capacitance....
My question is
(1) If I isolate the housing from the gnd, does it be affacted by EMI easily? Does it be an odd design?
(2) How much parastic capacitance should be taken in account?
Is there anybody giving me some idea?
mkchan