I'm trying to design 4 bit division circuit and used a comparison and subtraction technique to reach the answer. The logic is correct but the code has some bugs. The waveform is not correct. Can someone look into the code and waveform and say whats the problem is
I'm afraid you can't have it both ways. If the logic is correct then, by definition, IT HAS NO BUGS.
I haven't looked that closely at your code, but two things stand out to me:
1) Why isn't this a clocked process?
2) Why aren't there any comments?
You can't expect someone to look at your code and just figure out what you're trying to do without a few hints. In fact, when you go back and look at this in a few months, even you won't know what you were thinking when you wrote. How on earth do you expect us to know what your waveform is supposed to be? What's driving those signals? Nothing I can see.
And what the heck is this?
q,rut std_logic_vector(3 downto 0)
Well worse yet the simulation usually shows something entirely different than the logic that synthesis will produce when your sensitivity list uses signals that aren't even used in the process. Synthesis ignores the sensitivity lists.
Learn how to use a sensitivity list to wake up a process in VHDL. Whenever any of the signals in the sensitivity list changes, the process will by executed.
vhdlwhiz.com
I think you should also learn on how to write sequential and combinatorial logic.