Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Divider implementation

Status
Not open for further replies.

ivlsi

Advanced Member level 3
Advanced Member level 3
Joined
Feb 17, 2012
Messages
883
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Visit site
Activity points
6,868
Hi All,

What's the optimal implementation of a divider (one number divided by another) using a pure or registered logic? I mean flops, shift registers, logic gates, etc...

The divider might be clocked or not...

What is a parallel divider? What is a serial divider?

Thank you!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top