Black Jack
Full Member level 4
divide by 1.5 counter
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity divide1_5 is
port
(
clk : in std_logic ;
reset : in std_logic ;
div : out std_logic
);
end divide1_5;
architecture struct of divide1_5 is
signal d, q : std_logic_vector (1 downto 0);
-- signal q : std_logic_vector (1 downto 0);
signal fb : std_logic;
begin
process (clk, reset)
begin
if (reset = '0') then
q(0) <= '0';
elsif (clk'event and clk = '1') then
q(0) <= d(0);
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
q(1) <= '0';
elsif (clk'event and clk = '0') then
q(1) <= d(1);
end if;
end process;
fb <= NOT(q(0) OR q(1));
d(0)<= fb;
d(1)<= fb;
div <= fb;
end;
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity divide1_5 is
port
(
clk : in std_logic ;
reset : in std_logic ;
div : out std_logic
);
end divide1_5;
architecture struct of divide1_5 is
signal d, q : std_logic_vector (1 downto 0);
-- signal q : std_logic_vector (1 downto 0);
signal fb : std_logic;
begin
process (clk, reset)
begin
if (reset = '0') then
q(0) <= '0';
elsif (clk'event and clk = '1') then
q(0) <= d(0);
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
q(1) <= '0';
elsif (clk'event and clk = '0') then
q(1) <= d(1);
end if;
end process;
fb <= NOT(q(0) OR q(1));
d(0)<= fb;
d(1)<= fb;
div <= fb;
end;