Divide a signal at 9GHz using DFF-based divider in 45nm.

0.18um divider ghz

Hi guys,

I have implemented a ring oscillator at 45nm technology node. The ring oscillator has 11 stages of inverter, and the speed of the ring oscillator is 9GHz. The output is connected to a DFF-based divider, also at 45nm technology node, and the frequency is divided by 2 nicely. But all these are only in Spectre simulation. I wonder if in real world that the DFF-based divider can divide that range of frequency (8GHz ~ 11GHz).

I have done more simulation on the DFF-based divider, and it is shown that the divider could divide frequency of up till 12GHz.

In 45nm technology node, VDD is 0.9V.

Thank you!!

Added after 2 hours 57 minutes:

Will there be any kind of high speed problem?
Will there be like inductance, capacitance, or resistance problem?

Sorry I am not good in analog design.

Thanks.

dff divider

Professional-product implemented- design of a TPSC divider by 2 in 065CMOS have been developed with a max freq of 6.2GHz (Design of Experiment -DOE- Post Layout simulation) and measurements are in accordance with simulation.
Take care: there could be a LARGE difference from schematic and Layout simulations. Layout is really critical, something that have to be done at very high professional level.
Of course there will be a lot of parasitic problems...
I hope it can help.
Mazz

dff-based frequency divider

wuwoze said:

Will there be any kind of high speed problem?
Will there be like inductance, capacitance, or resistance problem?

Click to expand...

It's clearly possible to design an 8-11GHz frequency divider on a 45nm process. Lots of people have done it. The only issue is whether or not *your* design is good enough to operate at those frequencies.

Like Mazz said, you need to do simulations based on extracted, post-layout netlists. The difference between schematic and post-layout simulations can account for a couple of GHz worth of bandwidth.

Here is a paper on a 5.8GHz D-FF divider implemented on a 0.18um process. If you follow a similar design, you should be able to handle 8-11GHz without too many problems.

Thank you so much for your advices.

Man, I have a really really bad feeling. I should have increased the stages of ring oscillator.

The layout of divider is average, though I tried to minimize as much routing as possible.

It turns out that in post-sim the 11-stage-inverter ring oscillator can only run 5.6GHz, and the divider-by-2 can handle 6.25GHz signals.

But the ss divider cannot handle tt or ff ring oscillator. But their instance is at most 60 micron.

for dynamic latches; the divider has a lower frequency limit as well as the high frequency one , depending on the input signal amplitude/frequency , there is a paper talking about this issue by michael green ,