Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

divide a number in vhdl

Status
Not open for further replies.

rumi29

Junior Member level 1
Joined
Mar 17, 2011
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,418
Below this text there's a code and I have a problem. I'm trying tod divide a number per 10, because I want to make the table of the numbers just from "0" to "9" but the compilator its saying that I cannot use the operator "/"...and I don't know why...Thanks guys :D

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity LUT1 is
port(
clk: in std_logic;
led: out bit_vector(6 downto 0);
entrada: in std_logic_vector(5 downto 0));
end LUT1;

Architecture table of LUT1 is

constant max: integer := 50000000;--This are just for the first process
constant half: integer := max/2;--This are just for the first process
signal newclk: std_logic;--This are just for the first process
signal count: integer range 0 to max;--This are just for the first process

shared variable bcd: std_logic_vector (2 downto 0):="000";--This are just for the second process
shared variable aux: integer;--This are just for the second process
constant deu: std_logic_vector(5 downto 0):="001010";--constant to divide per 10 in binary


begin

divide: process--This process its only to divide the main clock of the main board.

begin
wait until clk'event and
clk='1';
if
count<max then count<=count + 1;
else count <= 0;
end if;

if count < half then newclk<='0';
else newclk <='1';

end if;

end process divide;

conv: process (newclk)--This process works like we shown you the last time, it's showing the number that you are entering by the switches but this time we just want to divide the number from the switches per 10 and then show the number.
begin


bcd := entrada / deu;-- Here we have the problem, we cannot divide this variable per 10, you know why? The compilator says that this operator "/" is not valid

case bcd is
when "0000000000000000" => LED <= "1000000";--0
when "0000000000000001" => LED <= "1111001";--1
when "0000000000000010" => LED <= "0100100";--2
when "0000000000000011" => LED <= "0110000";--3
when "0000000000000100" => LED <= "0011001";--4
when "0000000000000101" => LED <= "0010010";--5
when "0000000000000110" => LED <= "0000010";--6
when "0000000000000111" => LED <= "1111000";--7
when "0000000000001000" => LED <= "0000000";--8
when "0000000000001001" => LED <= "0010000";--9
when "0000000000001010" => LED <= "1000000";--10
when "0000000000001011" => LED <= "1111001";--11
when "0000000000001100" => LED <= "0100100";--12

--- ...until 100

when others => LED <= "1000000";
end case;
end process conv;
end table;
 

permute

Advanced Member level 3
Joined
Jul 16, 2010
Messages
923
Helped
294
Reputation
588
Reaction score
267
Trophy points
1,343
Activity points
8,543
is "/"(a,b) defined for unsigned values? I'm guessing it isn't. Further, you would need synthesis support for inferred division, as well as shared variables.
 
  • Like
Reactions: rumi29

    rumi29

    points: 2
    Helpful Answer Positive Rating

rumi29

Junior Member level 1
Joined
Mar 17, 2011
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,418
you mean that maybe I have to transform "entrada" and "deu" to unsigned variable? and also I need more variables to do the division?

Can you write in vhdl what are you suggesting?
 

lucbra

Advanced Member level 2
Joined
Oct 30, 2003
Messages
514
Helped
73
Reputation
146
Reaction score
63
Trophy points
1,308
Location
Belgium
Activity points
3,251
No, the division is not support as such in any synthesis tool.
Divide by 2, 4, 8, ... will work as this synthesizes to a shift right.

A division by 10 will need to be implemented with an other algorithm. I can refer to 'non-restoring division algorithm'.

Do you actually need to divide by 10 or 100?

Maybe this if .. then ... else can bring solution

in pseudo code:
if < 10
digit10 = 0
digit = number
else if < 20
digit10 = 1
digit = number - 10
else if < 30
digit10 = 2
digit = number - 20
and so on ...
 
  • Like
Reactions: rumi29

    rumi29

    points: 2
    Helpful Answer Positive Rating

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,025
Helped
2,058
Reputation
4,133
Reaction score
2,010
Trophy points
1,393
Activity points
38,602
you can use / if you use the numeric_std package. but then its not recomended because divide requires several pipeline stages, that you can't get with a divide function. you will need to use a divide ip block, which is usually provided by your vendor.
 
  • Like
Reactions: rumi29

    rumi29

    points: 2
    Helpful Answer Positive Rating

rumi29

Junior Member level 1
Joined
Mar 17, 2011
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,418
If I convert "entrada" to Integer then divide it by 10 and then convert it back to std_logic??? because sounds stupid that this device cannot divide per 10...
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,025
Helped
2,058
Reputation
4,133
Reaction score
2,010
Trophy points
1,393
Activity points
38,602
you can do that, but its still not recomended. it won't work very fast. divides that are not a bit shift are slow
 
  • Like
Reactions: rumi29

    rumi29

    points: 2
    Helpful Answer Positive Rating

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
47,443
Helped
14,036
Reputation
28,325
Reaction score
12,686
Trophy points
1,393
Location
Bochum, Germany
Activity points
275,942
The problem is here
The problem is not there. It has been explained in detail, that std_logic_arith respectively std_logic_unsigned don't recognize the divison operator. ieee.numeric_std in contrast does. In addition, the synthesis tool must be able to "infer" divider IP, which is mostly the case. With the old synopsys libraries, division is however suppported for integer, so there is a possible workaround.
 
  • Like
Reactions: rumi29

    rumi29

    points: 2
    Helpful Answer Positive Rating

jimmy_tag

Member level 2
Joined
Jul 19, 2010
Messages
49
Helped
8
Reputation
16
Reaction score
8
Trophy points
1,288
Location
India
Activity points
1,609
The problem is not there. It has been explained in detail, that std_logic_arith respectively std_logic_unsigned don't recognize the divison operator. ieee.numeric_std in contrast does. In addition, the synthesis tool must be able to "infer" divider IP, which is mostly the case. With the old synopsys libraries, division is however suppported for integer, so there is a possible workaround.
Its also one of the problem... u cant assign 5-bit signal to 3-bit signal. and its obvious you should use numeric_std.

I agree with FvM about the libraries support.
 
  • Like
Reactions: rumi29

    rumi29

    points: 2
    Helpful Answer Positive Rating

rumi29

Junior Member level 1
Joined
Mar 17, 2011
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,418
Thanks guys for your help! now its working :D
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top