Discussion: Specifying timing constraint on FPGA design

[saho]

hello.

I am newbie to FPGA technology implementation.

Reading papers on static timing analysis, it appears to me that implementing a design (into an FPGA) without specifying the timing constraint (arrival time, required time, false path, multi-path, ..) will result in a NOT-SO-GOOD performing circuit, when comparing with the design implementation (i mean, -> synthesis) with clear specific and rational timing constraint.

Great.

However, how does one come out with these figures( arrival time, required time,...) which are required when using a timing driven synthesis tools. Any hints? It is NOT so clear to me where to find out these values. I am thinking of an FPGA device databook. Am i missing something?? Or it is a trial-and-error attempt. Can you offer your experience and techniques with me.


SAHO

 

[xfpgas]

There are several ways to specify Timing Constraints in an FPGA.
I am familiar with Xilinx.

You can sepcify Timing COnstraints in the Xilinx Back End tools after synthesis. You can look here for more info here.
**broken link removed**

Most of the Synthesis tools let you specify the Timing Constrains at the RTL level as well. Refer to this document for Synplify Pro
**broken link removed**

It can also be a trial and error sometimes. For most of the designs, you dont really have to tweak much to meeting Timing. The tools usually do a good job. But if you are trying to get the maximum performace, looking for few more ns,then you should consider Timing Constraints. And ofcourse, that is not going to gaurantee that the Tools will meet those constrains. Atleast you can identify Critical Paths. And then go back and change your constrains, or worse, you might have to change a part of your RTL design, or better floorplanning.

But as I mentioned, for most of the designs, you are more than likely to meet Timing with out lot of tweaking. For some designs, trying to squeeze in few more ns, it is more than pressing one Button and letting the tools do the work. You have to guide these tools by applying appropriate Constrains. ANd these constraints differ from Vendor to Vendor. So you have to read the documentation of your vendors to get more information.

Hope this helps,
Kode

 

[saho]

Hello KODE:

Thank you for your insights.

Here is my flowchart for FPGA implementation. Assuming that the RTL written is synthesisable and fully tested in simulation! Hehe!!!!

Point 1 -Synthesis without timing constraint
=====
Ok, I could understand that synthesize a design with simply providing the global clock frequency may be sufficient (i.e., no timing constraint [may not the correct term, but you know what I mean!] is provided upfront to the synthesis. Following specifying the global clock, you can begin to compile and synthesize your design in the EDA synthesis tools. Looking at the report after the completion of the synthesis run, you may have circuit that meets your desired operating frequency. Great.

If design falls apart during synthesis (failing in meeting the desired operating clock with setup/hold violation), GO to Point 3 and uses timing constraint to optimise the design (not functionality!) so that it meets timing closure. Succeeding Point 3, you can then proceed to Point 2.

Point 2 -Importing EDIF into FPGA Vendor tools for Place&Route (i use the =====
term FPGA implementation).

After successfully synthesizing our design (without timing contraint), you can be begin to Place and Route the circuit inside the target FPGA technology. ONE QUESTION: do i need to specifying any timing here? I am thinking only about pin allocation, and nothing else. Since I have specify the global clock of my design during the synthesis process flow. Anything that I missed???

At the end of Place & Route, if the design meets requirements,; i.e, no negative SLACK TIME. SUPERB. You may then proceed to FPGA bitfile download to check if the design ACTUALLY works. ONE QUESTION HERE: If the the final design passed the Place & Route stage with no error, is the design bound to works (maybe not perfectly since there may be some corner cases which may not fully accounted in the simulation of the design).

Point 3 - Further Improvement on "Working" Design
To further improvement (as all Engineers do) the design so that it uses less logic and runs faster, you could achieve these improvement through the usage of timing constraint.

Reading XILINX technical note, it is suggested the circuit design performing better (with timing contraint applied). Reasons are that the combinational (combinatorial) logic between registers are optimised (in order to meeting user timing constraint). HOWEVER, the design functionality is NOT COMPROMISED. It is noted (using FPGA floorplan viewer) that design that uses timing contraint have its related logic closely packed and placed closer to the I/O pin to minimise delay, in constrast to the rather "loosely" placement of related logic (design with no timing constraint) inside the FPGA chip.


What are your thoughts???

 

[saho]

Hello KODE and others FPGA users

Tell about your FPGA implementation flow. I am listening. Hehe.

When do you decide to apply timing constraint for the design when the FPGA implementation stage? I understand the need and the importance of timing constraint on quality of Result of the synthesised design. I have difficulties in deciding the values to be used.

If you are using timing constraint, can you tell me how you arrive/decide the values to be input into the timing constraint manager.


Please share your experience with me and others that reading this forum

SAHO

 

[r_e_m_y]

Hi all,

Here are some of my experience in timing constraints ...
1) internal constraints
If all registers of your design are clocked by the global clock, you may not have to specify internal delay or setup ... Or you have very big combinatory process before clocking.
2) external constraints
This may be studied at the beginning of the design. You have to check all the components connected to your FPGA. For the FPGA outputs, Check the data sheet timings of your components (ex : data setup before chip select, data hold time ...), calculate the worst case and then specify the clock to pin delay into your synthesis/layout tool. For the Inputs, check that the setup time of the input registers are verified. If signals are not synchronous with the global clock, you may put 2 cascaded registers to avoid metastability.

 

[saho]

Hello REMY.

Can you elaborate and illustrate your teaching using a real life example?

Or, Do you /are you aware of any book that teaches these principles?

In brevity, I could sort of conceptualise your explanation. An example would be helpful and more educational.

Let me know. I want to be a good and hands-on FPGA designer.

SAHO