Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Discrepancy btw pole frequency calculated from DCop values and AC simulation results


Member level 2
Jun 3, 2008
Reaction score
Trophy points
Activity points
#Spectre #Cadence

I was not able to get the pole frequency from DCop values of a simple circuit. I need to use the DCop values in order to verify my calculations used to govern my design process. This is also kind of required, or at least much welcomed in my thesis. Also knowing from where the performance limitation are coming from, has a huge value. With this question I ask you to help me figure out where is the source of this discrepancy. This question is basically equivalent to "How to derive MOS small-signal parameters for hand calculations?" with supplying a concrete example.

I believe it is related either to the my interpretation of the DCop capacitances or AC and DCop use completely different data. The latter would throw me off, since the two results should be different facets of the same thing: linearized values of the large-signal equations around the operation point. For the same reason I would expect results within a few percent accuracy compared to each other.

The simplest test case what I could imagine is measuring and calculating the output conductance of a common source amplifier, whose terminals are AC grounded by the voltage sources used to set the operation point.
An AC test voltage signal with unit amplitude is applied to the drain and the current of the test source is the output conductance of the transistor. This model is very simple, since the gate of the transistor is deactivated. If we consider low frequency behaviour, than the intrinsic gate will be shorted to AC through the series gate resistance.
The model for hand calculation is a parallel combination of gds and Cd = cgd + csd + cbd.
Using the DCop parameters I got an error of about 40% compared to the AC simulation, which is way too much. I would expect an error of no more than a few percent.

In order to test my assumption I got back to a "relatively" simple -- with nowadays standards -- model: BSIM v3.3, but I got similar results compared to a BSIM-IMG model. The "Spectre Circuit Simulator Components and Device Models Reference" states only that cdd is the total drain capacitance including intrinsic, overlap and fringing components and junction capacitance. I got the same value if I sum cgd, csd, cbd, so it seems OK. In a slightly different testbench, where the AC source was applied at the gate, the AC simulation matched the result of the "pz" analysis, therefore I trust the results of the AC analysis as well.

The OCEAN code I wrote for easy comparison:
procedure(zti_pole_calc(dev AC_source)
let( (gds gm cgd cdd Cload cload_ac pole_sim pole_calc gds_sim gds_calc wf)
	; wf = mag(VF(n_out))
	wf = mag(IF(AC_source))
	gds = OP(dev "gds")
	cdd = abs(OP(dev "cdd"))
	cgd = abs(OP(dev "cgd"))
	cload_ac = abs(value(deriv(imag(IF(AC_source)))/2/3.14159 xmin(xval(wf))))
	Cload = 0
	foreach( i list("cgd" "csd" "cbd") 
		Cload = Cload + abs(OP(dev i))
	printf("Dev.    gds   -   cdd   -   cgd   -   Cload   -   C_AC\n")
	printf("%s: %.2e - %.2e - %.2e - %.2e - %.2e\n" dev gds cdd cgd Cload cload_ac)

	gds_calc = gds
	gds_sim = value(wf xmin(xval(wf)))
	plot(wf ?expr list(dev))
	pole_sim = cross(wf gds_sim*sqrt(2) 1 'rising)
	pole_calc = gds_calc/Cload/2/3.14159

	printf("\n\t\tDC gain --- Pole\n")
	printf("sim:  %.2e\t%.2e\n" gds_sim  pole_sim)
	printf("calc: %.2e\t%.2e\n" gds_calc pole_calc)

procedure(zti_multi_dev_calc(l_dev l_out)
for( i 1 length(l_dev)
	zti_pole_calc(nthelem(i l_dev) nthelem(i l_out))	

Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com



Design Fast