Hi,
I need a diode varactor can integrate in IC, when add reverse bias voltage from 0~3v, the capacitance varies as large as possible.
For N+/Psub diode in standard CMOS process, when reverse bias voltage from 0~3v, capacitance vary only 2 times, how to get larger vary range?
Anyone has experience in CMOS process, could you share with me? Thanks a lot!
thanks for reply, could you explain more detail,
how about the process structure of the special varactor?
do you know which process fab have this special varactor IP?
Take a PN junction (both MOS and diode varactor), the capacitance changes when the depletion region is increased or decreased. When you increase the region, the electric field across this region increases. There has to be a limit before this junction enters breakdown. So foundries set a conservative limit for reliability issues.
Infineon offers a special varactor for their SiGe BiCMOS process (they use an extra doping layer to increase the tuning range). I don't have their designkit and so i can't check.