Digital logic sequence

[treez]

Hello, I wish to have a digitial output which basically goes 0,0,0,1,1,1,0,0,0,1,1,1,0,0,0,1,1,1.....repeatedly

Each comma indicates the circuit being clocked......

I wish to use logic gates and D types for this, do you know a method to get this?

 

[HTA]

You can yuse a shift register and load it every six clock cycles with the 000111 pattern. A counter can generate the load pulse.

Enjoy your design work!

 

[treez]

ok thanks, I know what you mean, but I wish to do the type of circuit that has 6 dtypes, and then the output bus of them is fed back to nand logic, and every time the dtypes are clocked,one of the d types will give the 000111000111000111.... output.

I used to do this easily years ago......I used karnaugh maps......for example, in this case I would have

000001 goes to 000111
000010 goes to 000111
000011 goes to 000111
000100 goes to 000111
000101 goes to 000111
000110 goes to 000111
000111 goes to 100011

etc etc.......you have the k maps, and something is on one side of them, and something else on the otherside, and then whats in the boxes is what you group up to minimise the logic.....and you can only group in certain ways etc.

Do you have a good reference for this?, to remind me back in to it?


the way with the counter will need too much auxiliary logic with the counter I think?

 

[HTA]

Another option is to use six D-Type flipflops and connect them as a closed loop 6 bit shift register. With power good you can clear the first three to "0" and the last three set to "1". Since it is cloosed loop you get the 000111 out as a repeated pattern when clocking.

For Karnaugh map you can check-out this: https://en.wikipedia.org/wiki/Karnaugh_map .

Enjoy your design work!

 

[treez]

thanks,
Ive just realised I can also do this as a sequencer...with the following sequence...

000
001
011
111

repeated.

Since its 3 bits, does that mean there will be 8 karnaugh maps?

And on the axes of the karnaugh maps....is it previous state on one side, and next state on the other side?


good old youtube for refreshing the brain cells.....here is that sequencer in NANDs and D Types....

 

[HTA]

A sequencer instead of a shift register is an option. You might also look at the total number of iC required for each solution.

Looks like you enjoy your design work!

 

[permute]

You can also use a Johnson counter:
https://en.wikipedia.org/wiki/Ring_counter

The logic is very simple. 3 FF's, 1 inverter.

 

[kranthi_vlsi]

Hello, I wish to have a digitial output which basically goes 0,0,0,1,1,1,0,0,0,1,1,1,0,0,0,1,1,1.....repeatedly

Each comma indicates the circuit being clocked......

I wish to use logic gates and D types for this, do you know a method to get this?

use johnson counter take output at first flop

 

[treez]

if I use Johnson I have to load it, and that means extra circuitry to load it properly

 

[andre_luis]

You could try perform this way :

Conter (modulo-3) -----> NAND 2x1 -----> D-FF

That means: Every time counter reach 11, a nand port generate a falling edge, triggering flip-flop.



+++

 

[permute]

the johnson counter has the following sequences:
000 001 011 111 110 100 -- 6/8 elements
101 010 -- 2/8 elements.

If you want you can add the feedback logic to force it into a correct state. eg, if the 2 msb = "10", reset (sync).
then you have the eventually periodic sequence 010 101 000 001 011 111 110 100 000 001 011 111 110 100 ...

for counters, you can also count from 1 to 6
001
010
011
100
101
110 (2 msb = load 001)

this could give the worst case 111 001 010 011 100 101 110 001 ...

 

[kranthi_vlsi]

if I use Johnson I have to load it, and that means extra circuitry to load it properly

no need of loading it...just use 3 bit johnson counter and reset it before using

intial state after reset is 000 den after 100,110,111,011,001,000 take output at lsb u will get the desired sequence 0,0,0,1,1,1