digital design using hardware description languages

[vaidhyanathan]

1.why we say an intra-statement delay is not synthesisable?
2. how an intra-statement delay is used in testing a design?

thanks in advance:-D

 

[yadavvlsi]

Delay values in HDLs are used for modeling hardware delay. When you write a behavioral code, delay values accounts for the gate delays. You will not find any delay construct in RTL code. It is used for simulation purpose. After synthesis you will have actual gates and their real delays.

 

[pavan.mk]

I agree with yadavvlsi. The delay constructs are not synthesizable, in the sense that, those values are required only during simulation where you test your RTL and observe the delay what you gave in the waveform. But once synthesis is done, the actual delay value of the gates and routing delay is calculated and these values are used in the hardware.