Digital design question..

[sp3]

Hi all,

I have a digital design question here.. Please look at the attachment..

I have the input for DFF as D. later this input is XORed with the Q (output of DFF). The XOR output is passed to a unkown circuitry so that I get the original input D. Now anyone of guys please let me what is the unkown circuit here ??

Thanks,
sp3

 

[shweta_eda]

simply xoring will give the previous input............isntit
the ckt will be xor gate........

 

[sp3]

Hi shweta_eda,

But that is fine for a Combo logic.. Here we have a D-FF, giving sampled output. So do I take care of this ?

Thanks,
sp3

 

[dipakg]

Hi Sp3,

I your unknown ckt is D-FF then you must consider there will be delay of 2 clks, after that you will get D value as your final output. I am attaching the ckt diagram.

Regards,
Dipak

 

[nand_gates]

Here the D FF and xor gate will act as edge detector for D input. If there is a change
on D input the circuit will produce a one cycle pulse. To get the original D input again
just connect the output from XOR to T FF.

 

[dipakg]

Hi nand_gates,

I didn't get you actually. Won't T-FF will give the output always as 1? Because the XOR output will always be 0 (D and Q are same). Please let me know if I am wrong?

Thanks,
Dipak

 

[nand_gates]

Here is the verilog code ... See it ur self.

// D FF and XOR gate circuit edge detector

module edge_detect(
   // Outputs
   d_event,
   // Inputs
   clk, reset_n, d
   );
   input clk, reset_n, d;
   output d_event;
   reg    q;
   assign d_event = d ^ q;
   always @(posedge clk or negedge reset_n)
     if (!reset_n)
       q <= 0;
     else
       q <= d;
   
endmodule // edge_detect

// Circuit to Regenerate D of above circuit (T-FF)

[code]module regen_d (
   // Outputs
   d_regen,
   // Inputs
   clk, reset_n, d_event
   );
   input clk, reset_n, d_event;
   output d_regen;
   reg  d_regen;
   always @(posedge clk or negedge reset_n)
     if (!reset_n)
       d_regen <= 0;
     else if (d_event)
       d_regen <= ~d_regen;
   
endmodule // regen_d

// Test bench to see the operation of circuits above
module test();
reg clk;
reg d;
reg reset_n;

wire d_event;
wire d_regen;
edge_detect edge_detect(
// Outputs
.d_event (d_event),
// Inputs
.clk (clk),
.reset_n (reset_n),
.d (d));
regen_d regen_d (
// Outputs
.d_regen (d_regen),
// Inputs
.clk (clk),
.reset_n (reset_n),
.d_event (d_event));
initial begin
clk = 0; d = 0;
reset_n = 0;
#33 reset_n = 1;
repeat(1000)
@(posedge clk) d <= #2 $random;
#100 $finish;
end

always #5 clk = ~clk;

endmodule // test
[/code]