Digital delay circuit simulation

[JKJoy]

Hello,
Can somebody give any circuit idea for designing a digital delay circuit.
This for simulating the possible delay during a serial communication using PIC microcontroller.

Thanks

 

[mrinalmani]

Delays in order of? s, ms, us, ns?

 

[JKJoy]

Delays in order of? s, ms, us, ns?

Delays in ms.

Thanks

 

[kripacharya]

Delays in ms.

Thanks

In a time period of just 1 mS an electrical signal can travel more than 200 Km ! I doubt your PIC serial signal will be used for this distance. I think you are looking for at most a sub- uS delay.

 

[mrinalmani]

If you want a temporary delay for simulation purpose only, an easy way would be to insert an RC delay.
For example if you want a delay of 1ms at the output of a port pin, connect a series RC to the port and tap the delayed output from across the capacitor. The output will be delayed by roughly 0.8 to 1 time constant.
So for 1ms 100 ohm and 10uF should serve the purpose.

 

[JKJoy]

In a time period of just 1 mS an electrical signal can travel more than 200 Km ! I doubt your PIC serial signal will be used for this distance. I think you are looking for at most a sub- uS delay.

That is correct. I am doing a wired FSK circuit. In which I sensed small delay (may be few uS) to receive the data with small distance cable. I presume the delay was contributed by the mod/demod circuits anyway. That is OK.
That is why I just wanted to simulate this, doubting may be in real lengthy cable environment, I may have increased delays.

Thanks

 

[JKJoy]

If you want a temporary delay for simulation purpose only, an easy way would be to insert an RC delay.
For example if you want a delay of 1ms at the output of a port pin, connect a series RC to the port and tap the delayed output from across the capacitor. The output will be delayed by roughly 0.8 to 1 time constant.
So for 1ms 100 ohm and 10uF should serve the purpose.

I will try this. But my doubt is whether this RC will destroy data shape and corrupt data. Anyway let me try it.
Thanks

 

[mrinalmani]

Think again... and this time carefully! Does it really!?

 

[kripacharya]

I will try this. But my doubt is whether this RC will destroy data shape and corrupt data. Anyway let me try it.
Thanks

The RC will definitely change the rise/ fall shapes of your signal. So if your application is edge sensitive, then you need to correct for this. One way would be to include some sort of schmitt gate with thresholds at appropriate levels to recover the edges.

 

[mrinalmani]

Mr. Kripachararya, do you mean that edge triggered devices demand a minimum dv/dt during rise and fall?

 

[JKJoy]

Hi mrinalmani,

I tried the RC method, but as suspected, the dv/dt kills the data. In oscilloscope, the 2400bps data is seen lost its nature.
With 100ohm and 10uF, the waveform is totally destroyed.

Thanks

 

[Gorgon]

If you want to simulate a long cable for communication, you should read the datasheet of the cable you will recommend for your application, and simulate with this calculated values of the components. You should also use the appropriate communcation standard, and drivers for this.

 

[kripacharya]

Mr. Kripachararya, do you mean that edge triggered devices demand a minimum dv/dt during rise and fall?

No.
I mean that if it is a synchronous comm's channel, then the clock edge must be well defined.

 

[mrinalmani]

JKjoy: I had assumed the data pulses to be much longer than the delay period. For eg. a delay of 1ms should have data pulses lasting more than, say, 4ms. The whole idea is to have a clear "flat" portion in the trapezoid of the the data pulse.
If the data pulses are smaller or comparable to the delay, a digital buffer seems to be the only solution.

 

[kripacharya]

Hi mrinalmani,

I tried the RC method, but as suspected, the dv/dt kills the data. In oscilloscope, the 2400bps data is seen lost its nature.
With 100ohm and 10uF, the waveform is totally destroyed.

Thanks

You have to choose your R and C depending on the amount of delay you want. But this delay should be not more than approx~ 40% of your bit period using this method.

So at 2400bps, you have to choose RC <= 0.4/2400, or < ~ 167uS (max)
This would be roughly the delay for a 40-50Km long cable. More than what you need I would think.

Now choose C = 100nF.
Then R (max) ~ 1.8K. And you can decrease R for smaller delays.

Try it out. As a wrote before, use a schmitt to straighten out the edges if required.

 

[FvM]

A digital delay in the same order of magnitude as the bit time or even larger can be best implemented as a digital shift register with respective high clock rate.

 

[JKJoy]

You have to choose your R and C depending on the amount of delay you want. But this delay should be not more than approx~ 40% of your bit period using this method.

So at 2400bps, you have to choose RC <= 0.4/2400, or < ~ 167uS (max)
This would be roughly the delay for a 40-50Km long cable. More than what you need I would think.

Now choose C = 100nF.
Then R (max) ~ 1.8K. And you can decrease R for smaller delays.

Try it out. As a wrote before, use a schmitt to straighten out the edges if required.

Thanks for the precise suggestion. It worked as you suggested. As you mentioned I am not going to have more than 3KM long cables. But I have some FSK circuits which may put in some delay and i suppose that may be only few uSecs.
Anyway I did simulate RC delay with the suggested values and added schmitt buffer to straiten the edges.

Thanks to Mrinalmani too for his similar valuable suggestions...

Regards