digital decimation filter for sigma delta ADC

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rakesh045

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i need to implement a sigma delta ADC with 12 bit resolution at the output.
The sigma delta design has the modulator part followed by the digital decimation filter.
i have constructed the modulator part in "system vision"
now i require the DIGITAL DECIMATION FILTER part in vhdl to complete the design.
Can somebody help me in how to construct the filter. it will be great if someone provides a vhdl code here
 

First you need to determine the frequency response of the filter, decimation factor, sample rates, etc. Then you can decide on what type of filter to implement first.
 

the frequency of my application is 50kHZ-sinusoidal waves.
i would require around 16 and at best 32 samples in a cycle so the sample rates should be around 1.6MHz at the output
we have not decided yet on the decimation factor required
what are the conventional types of filters used for this purpose?
 

Typically sinc, CIC, polyphase or half-band filters depending on your requirements.
 

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    rakesh045

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