digital correction for cyclic adc

[shamala]

Hi
I am designing a cyclic adc 8 bit. I am using 1.5 bit stage. unlike pipeline adc there is no flash adc for the last stage, so,
that i can get digital corrected code by directly adding them.

So, I need a RSD to binary conveter

i have seen a RSD to binary converter in this paper

B. Ginetti, P.G.A. Jespers, and A. Vandemeulebroecke, “A CMOS 13-b cyclic RSD A/D converter”
IEEE Journal of Solid-State Circuits, vol. 27, pp. 957–964, July 1992.

according to this paper considering 4bit for Vx(Vin) slightely greater than 0V (fullscale range Vref to -Vref,)
gives code 00000 in 2's compliment, which is not equal to 1000

 

[A.jafari]

Hi.
I read that file that you mentioned but a thing that you said is completely wrong.
to using 1.5 bit gain stage you need to have a 1 Bit flash ADC which compare the last output of your mdac with 0 voltage.