andrea_mori
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I'm new in FPGA design, so I need some suggestions.
I would build a digital audio player with the following characteristics:
- it should read data from SD card only
- SD card will be formatted FAT32
- the root of SD card will contain folders only (named as album title/artist)
- no subfolders will be allowed on SD card
- each SD card folder will contain wav files only (named as title track)
- only 16 bit / 44.1 kHz wav files will be allowed
- 7 buttons have to be managed: previous track, next track, play, stop, pause, return and enter to navigate the folders
- TFT display will be managed (preferably touch) to show album/artist, title track, time elapsed and so on
- data output (16 bit serial X 2 channels) should feed a r-2r discrete ladder DAC
- 74XX595 logic will split the serial data to parallel to feed the ladder network
- master clock should be 11.2896 MHz, shared from both DAC logic and FPGA, to avoid any divider (to minimize jitter)
- every time a single bit is ready, FPGA should enable the 595 to store it (595 clock enabled from FPGA in sync with master clock)
- every time 16 bit for 2 channels are read, FPGA in sync with master clock should enable the 595s to output parallel data to update the ladder network
Since I have to buy a FPGA evaluation kit to start experimenting
what device do you suggest?
do I need simple FPGA or FPGA with ARM embedded?
Thanks
I would build a digital audio player with the following characteristics:
- it should read data from SD card only
- SD card will be formatted FAT32
- the root of SD card will contain folders only (named as album title/artist)
- no subfolders will be allowed on SD card
- each SD card folder will contain wav files only (named as title track)
- only 16 bit / 44.1 kHz wav files will be allowed
- 7 buttons have to be managed: previous track, next track, play, stop, pause, return and enter to navigate the folders
- TFT display will be managed (preferably touch) to show album/artist, title track, time elapsed and so on
- data output (16 bit serial X 2 channels) should feed a r-2r discrete ladder DAC
- 74XX595 logic will split the serial data to parallel to feed the ladder network
- master clock should be 11.2896 MHz, shared from both DAC logic and FPGA, to avoid any divider (to minimize jitter)
- every time a single bit is ready, FPGA should enable the 595 to store it (595 clock enabled from FPGA in sync with master clock)
- every time 16 bit for 2 channels are read, FPGA in sync with master clock should enable the 595s to output parallel data to update the ladder network
Since I have to buy a FPGA evaluation kit to start experimenting
what device do you suggest?
do I need simple FPGA or FPGA with ARM embedded?
Thanks