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Digilent Parallel Interface Model

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madalin1990

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Hi!

I am trying to run the "Digilent Parallel Interface Model Reference" from Digilent but i found a mismatch between the entity ports and the .ucf . Although in the .ucf file there is an "rgan" signal assigned to FPGA's pins this signal is never present in the vhdl entity.

Has anyone happened to encounter this problem before?


I will atach the vhdl file and an archive containing .ucf files for different FPGAs.

View attachment DpimRefUcf.zip View attachment dpimref.txt
 
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