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Differential signalling confusion

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dany.1986

Junior Member level 1
Hi

I have a problem understanding how a differential signalling works. I have combined two most common graphical explanations about differential signalling into the attached picture. My questions are:

Do V+ and V- correspond to the nets pointed in the picture by the red arrows?
If VOD is 0.350 V max, and VOS is 0.7 V min and 1.2 V max then is it correct to calculate VOH and VOL as follows:
VOH= VOS max + |1/2*VOD max| so VOH= 1.2 + |1/2*0.350|= 1.325 V ???
VOL= VOS min - |1/2*VOD max| so VOL= 0.7 - |1/2*0.350|= 0.575 V ???

In the current configuration (the one in the top of the picture) the receiver sees that V+ is 1.325 V and V- is 0.575 V and interprets it as logic '1' ???
If the mosfets referenced by the negative sign are closed then does it mean that V + becomes 0.575 V and V- becomes 1.325 V so that the receiver will interpret it as logic '0' ???

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• differential_signalling.jpg
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In the current configuration (the one in the top of the picture) the receiver sees that V+ is 1.325 V and V- is 0.575 V and interprets it as logic '1' ???
If the mosfets referenced by the negative sign are closed then does it mean that V + becomes 0.575 V and V- becomes 1.325 V so that the receiver will interpret it as logic '0' ???

Didn't check if your voltages are correct, but the interpretation of what is considered a logic 1 and logic 0 is correct.

dany.1986

dany.1986

Points: 2
Is the differential receiver just a differential op amp or can it be/is it a comparator?

Usually a comparator, because we are only interested in digital on/off type signals.

dany.1986

dany.1986

Points: 2
This high speed logic for 3.3V known as Low Voltage Differential Signalling LVDS or DS for short.

It is a switched current sourced logic that supports 400 Mbps serial channels with very low timing skew (50ps diff.), often used for graphic data interfaces from mobile motherboard to lid LCD decoder.

https://www.ti.com/product/ds90lv028a&lpos=See_Also_Container&lid=Alternative_Devices

When you get to these speeds and well beyond, DS and then current mode logic CML, is preferred for symmetry and fast rise times, low skew , low latency.

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