Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Differential Pair Transconductance!!!

Status
Not open for further replies.

saad

Advanced Member level 4
Joined
Jun 8, 2005
Messages
101
Helped
10
Reputation
20
Reaction score
7
Trophy points
1,298
Location
Pakistan
Activity points
2,080
Hi Everyone!!!
I am using pMOS input differential pair in a single stage opamp. I want to increase the transconductance (gm) of the input pair. I increase aspect ratio (W/L) to decrease Vdsat; hence expecting gm to increase.

On the other hand; Vds drop is decreased whereas Vdsat and gm remain almost unaffected (simulation results are given below). How can I keep Vds constant or increase gm instead? Can anyone help?

W/L = 60

Name: m1

Model: cmosp

Id: -9.90e-05

Vgs: -9.39e-01

Vds: -5.28e-02

Vbs: 0.00e+00

Vth: -5.07e-01

Vdsat: -3.59e-01

Gm: 2.15e-04

Gds: 1.73e-03

Gmb 8.41e-05

W/L=120

Name: m1

Model: cmosp

Id: -9.95e-05

Vgs: -9.14e-01

Vds: -2.70e-02

Vbs: 0.00e+00

Vth: -5.08e-01

Vdsat: -3.44e-01

Gm: 2.25e-04

Gds: 3.54e-03

Regards,
Saad
 

DenisMark

Full Member level 6
Joined
Sep 16, 2005
Messages
325
Helped
104
Reputation
208
Reaction score
34
Trophy points
1,308
Location
Russia
Activity points
3,437
How I can see ur pmos input transistors work in triode regione (Vds too low). It seems something is wrong in ur circuit or in testbenches.
U should to bias input pair in saturation region, ever they need to work in weak inversion (sub-threshold, |Vgs-Vth|<=-50mV). In weak inversion Gm=Id/(n*Vt), n=1.3..1.5, Vt=kT/q. So futher increase of Gm is only achivable with Id increasing.
I give u usefull reference, i think they will be usefull to u.
https://www.edaboard.com/viewtopic.php?p=762910#762910
https://www.edaboard.com/viewtopic.php?p=621110#621110
 

saad

Advanced Member level 4
Joined
Jun 8, 2005
Messages
101
Helped
10
Reputation
20
Reaction score
7
Trophy points
1,298
Location
Pakistan
Activity points
2,080
DenisMark said:
How I can see ur pmos input transistors work in triode regione (Vds too low). It seems something is wrong in ur circuit or in testbenches.
U should to bias input pair in saturation region, ever they need to work in weak inversion (sub-threshold, |Vgs-Vth|<=-50mV). In weak inversion Gm=Id/(n*Vt), n=1.3..1.5, Vt=kT/q. So futher increase of Gm is only achivable with Id increasing.
I am biasing differential pair with constant current source (100uA) and you can see the operating current is 99uA (and it seems to me that device is operating in saturation).

What do u think?

I have attached the opamp schematic too. I am getting extremely poor gain (dont know whats wrong :cry:) Please check if cascodes in the gain stage are biased correctly or not?

Regards,
 

DenisMark

Full Member level 6
Joined
Sep 16, 2005
Messages
325
Helped
104
Reputation
208
Reaction score
34
Trophy points
1,308
Location
Russia
Activity points
3,437
It isn't clear. What voltage values at gate, source, drain nodes?
May be common mode voltage at inputs of opamp is too low. For ur circuit the bottom ICMR is VgsN(M3,M4)-VthP(M1,M2). I can suggest that u set input to ground potential (but ur circuit don't allow this) or overdrive voltage of NMOS is too high(increase W/L ratio of NMOS).
 

saad

Advanced Member level 4
Joined
Jun 8, 2005
Messages
101
Helped
10
Reputation
20
Reaction score
7
Trophy points
1,298
Location
Pakistan
Activity points
2,080
I have set W/L of M3,4 to be same as W/L for M10 (for proper mirroring) to be 5.

How would W/L of M10 affect the output resistance and hence gain of the amplifier??? Gain is really poor (Av=10) :cry::cry::cry::cry::cry:

Please see if i m biasing cascodes right or not??
 

DenisMark

Full Member level 6
Joined
Sep 16, 2005
Messages
325
Helped
104
Reputation
208
Reaction score
34
Trophy points
1,308
Location
Russia
Activity points
3,437
Biasing of cascode don't have influence of PMOS pair operation point. At the picture all looks ok. M14 and M18 must have lager W/L ratio than M9,M10 and M7,M8 so that devices operates in saturation ever in worst case (max current, max temperature).
U must provide me operation point information regarding M1,M3 and voltages at their terminals to resolve ur primary problem.
 

tirnanog

Newbie level 3
Joined
Sep 10, 2007
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,294
As DenisMark has already asked: What is your common mode input voltage?
If this is too low then devices M1 & M2 would be out of saturated region and acting just as switches with low output impedance giving you low gain.
 

saad

Advanced Member level 4
Joined
Jun 8, 2005
Messages
101
Helped
10
Reputation
20
Reaction score
7
Trophy points
1,298
Location
Pakistan
Activity points
2,080
In order to keep M9 in saturation its gate voltage must be Vt+Vdsat above its source voltage (i.e. Vdsat10). (W/L) of M14 is (1/5)(W/L)of M9 forcing Vg14 to be above Vt+2Vdsat hence keeping M9 to be in saturation.


Please correct me if i am doing it wrong!!

i can post node voltages of most of the transistors in the amplifier in some time. till then please check if i m correctly considering biasing??

Thanks
 

DenisMark

Full Member level 6
Joined
Sep 16, 2005
Messages
325
Helped
104
Reputation
208
Reaction score
34
Trophy points
1,308
Location
Russia
Activity points
3,437
It's correct, but u should check this condition over PVT and in worst case.
Give me operation point information regarding M1,M3 and voltages at their terminals to resolve ur primary problem.
 

saad

Advanced Member level 4
Joined
Jun 8, 2005
Messages
101
Helped
10
Reputation
20
Reaction score
7
Trophy points
1,298
Location
Pakistan
Activity points
2,080
tirnanog said:
As DenisMark has already asked: What is your common mode input voltage?
If this is too low then devices M1 & M2 would be out of saturated region and acting just as switches with low output impedance giving you low gain.
For AC analysis, I am using 1V AC signal.
 

tirnanog

Newbie level 3
Joined
Sep 10, 2007
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,294
What is the dc voltage that is being applied at the gate of M1 and M2?
 

saad

Advanced Member level 4
Joined
Jun 8, 2005
Messages
101
Helped
10
Reputation
20
Reaction score
7
Trophy points
1,298
Location
Pakistan
Activity points
2,080
DenisMark said:
U must provide me operation point information regarding M1,M3 and voltages at their terminals to resolve ur primary problem.
Here are the node voltages (attachment). I m using 1V AC signal for AC analysis.

Please check if something is wrong.

W/L of all the transistors are as follows

M1,M2 = Kc
M3,M4,M6,M9,M10 = Kb
M14,M16,M19 = Kb/5 (for proper biasing)
M17 = Ka/5 (for proper biasing)
M5,M7,M8 = Ka
M11,M12,M13,M18 = 2*Ka

where Ka=15, Kb=5, Kc=60
See if anything is problematic!!

Thanks
 

saad

Advanced Member level 4
Joined
Jun 8, 2005
Messages
101
Helped
10
Reputation
20
Reaction score
7
Trophy points
1,298
Location
Pakistan
Activity points
2,080
tirnanog said:
What is the dc voltage that is being applied at the gate of M1 and M2?
It will be short circuited for AC analysis anyways.. does applying DC voltage matter?? atleast i dont think so
 

tirnanog

Newbie level 3
Joined
Sep 10, 2007
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,294
Yes.

From looking at the operating point information that you provided it looks like you have a dc voltage of 0V at the gate of M1 and M2 and I think that is your problem. This voltage needs to be higher. How do you setup the input stimulus?
 

DenisMark

Full Member level 6
Joined
Sep 16, 2005
Messages
325
Helped
104
Reputation
208
Reaction score
34
Trophy points
1,308
Location
Russia
Activity points
3,437
Ok, VgsM3=0.996V and VthM1=0.508 so minumum of ICMR is VgsM3-VthM1=0.488V. So if dc voltages on the gates of M1 & M2 low than 0.488 their will enter in triode region.
It looks like u don't build testbench correctly. Yes, the inputs must be tied to AC ground and AC source must present in series with one of them, but it doesn't mean that the inputs must be connected to DC ground.
Apply DC source to positive input (more than VgsM3-VthM1 and low than Vdd-VgsM1-VdsatM11), short output and negative input through inductance 1H (short during DC analisys, open circuit during AC), short negative input to ground through capacitance 1F also (open - DC, short - AC). So ur input common mode voltage will be determinated by DC source. Place AC source. It doesn't matter in series to positive or negative input, it affect on initial phase shift only. Amplitude of AC source also doesn't matter, it only affect on output voltage amplitude, not the gain or phase, it can be 1V, 1kV, 1pV, etc.
After all do DC operation point and AC simulation. Difference between positive and negative inputs will be offset voltage.
If u want to decrease lowest boundary of ICMR u can tie bulk contacts of M1&M2 to supply rail. So u increase VthM1 due to body effect. If body effect is strong u can obtain ICMR begining from 0V.
 

srik10

Newbie level 2
Joined
Sep 26, 2007
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,289
Just curious,

Whats op-amp topology is this? looks like a diff pair followed by a Cascode + Folded cascode. Is that right ?

What is the advantage of using this over a folded cascode amp ??
 

rajanarender_suram

Full Member level 4
Joined
Jan 20, 2006
Messages
215
Helped
22
Reputation
44
Reaction score
9
Trophy points
1,298
Activity points
2,375
from your node voltages for M1 nad M2 vds<vdsat that means these transistors are in linear region.

Thats is you main problem

Added after 4 minutes:

what about the node volt of m11
 

tarun_taurus

Junior Member level 3
Joined
Feb 15, 2005
Messages
27
Helped
4
Reputation
8
Reaction score
3
Trophy points
1,283
Activity points
1,420
Ur transistors are in Triode region and you need to define DC for your gate. before starting AC analysis DC operating pt. is established.
as someone rightly suggested, you need to increase Gate voltage of PMOS to reduce VDSAT and Increase Vds.
u get poor gain because the transistors are running in triode region.
Do .OP analysis before doing any other analysis & ensure transistors are in saturation.

--
Mt
 

ftxhh

Newbie level 2
Joined
Oct 27, 2007
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,292
Hi saad,
As suggested, the input pmos pairs are in triode region, cause vdsat=0.34v and vds=0.0203v,which is lower than vdsat. I think you can increase the input pmos's bias voltage.
Best regards!
 

rania_hassan

Advanced Member level 4
Joined
Apr 29, 2005
Messages
104
Helped
9
Reputation
18
Reaction score
1
Trophy points
1,298
Location
Egypt
Activity points
1,764
I don't prefer the usage of PMOS as input diff pair as it needs larger W/L to get the same gm that can be achieved by smaller NMOS
so it really limits your max operating frequency
best regards,
Rania
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top