Differential MOS amplifier

[furiaceka]

Hi,
I have this type of circuit to analyze:

1) What is the kind of topology of this circuit? because it is similar to a OTA fully diff but there are 2 differential pairs(M7-M8 and M1-M2), one with Vo and another with differential and common input
2) What is the differential gain Ad?

if you have any link with explanation of this circuit I'm very happy to read it.

 

[nitishn5]

Hi,

This is a simple 2 stage filly differential Opamp.
Input at the gates of M1-M2 and Output across R_L.

There is only one differential input pair, M1-M2.

M1-M2 is the input transistors with M3-M4 as the current source load. The current is defined by the bias circuit involving M9-M10 and Ib.

M7 and M8 is the current source load for the second stage. The second stage input pair is M5-M6.

The gain for the first stage would be
A1 = 2 x g_m-1,2 x (r_o-1,2||r_o-3,4)

The gain for the second stage would be
A2 = 2 x g_m-5,6 x (r_o-5,6||r_o-7,8)

Total gain would be the product of the individual stage gains.

 

[furiaceka]

Hi,

This is a simple 2 stage filly differential Opamp.
Input at the gates of M1-M2 and Output across R_L.

There is only one differential input pair, M1-M2.

M1-M2 is the input transistors with M3-M4 as the current source load. The current is defined by the bias circuit involving M9-M10 and Ib.

M7 and M8 is the current source load for the second stage. The second stage input pair is M5-M6.

The gain for the first stage would be
A1 = 2 x g_m-1,2 x (r_o-1,2||r_o-3,4)

The gain for the second stage would be
A2 = 2 x g_m-5,6 x (r_o-5,6||r_o-7,8)

Total gain would be the product of the individual stage gains.

Thank you for your fast reply.
So it' equal to this other circuit: (the only difference is that M5,M6 are pMos instead of nMos, what is change??)


So in this case the total differential gain is:

A_TOT = 2 x g_m1 x (r_o1||r_o3) x g_m5 (r_o5||r_o7)

it's correct?

Thanks in advance

 

[nitishn5]

Sorry but I didn't notice that M5-M6 were NMOS in the first circuit. In that case the second stage would not have any gain since it is just Source follower(buffer). Therefore the total gain would be the gain of the first stage alone.
Also the first circuit does not have any common mode rejection.

The second circuit is indeed a proper OTA with common mode rejection because of the tail current in the first stage. The equation for gain given by you is also correct.

PS the circuit diagram for the 2nd circuit shows that the inputs are given without any common mode unlike in the 1st circuit with Vc+Vd/2 and Vc-Vd/2. But the 2nd circuit would also require a minimum common mode for the circuit to operate.

 

[furiaceka]

Sorry but I didn't notice that M5-M6 were NMOS in the first circuit. In that case the second stage would not have any gain since it is just Source follower(buffer). Therefore the total gain would be the gain of the first stage alone.
Also the first circuit does not have any common mode rejection.

Ok thanks!
So M5-M6 is a source follower to optimize the transfer of energy to load, and M7-M8 are the biasing transistor of the source follower stage.
It is correct?

The second circuit is indeed a proper OTA with common mode rejection because of the tail current in the first stage. The equation for gain given by you is also correct.
PS the circuit diagram for the 2nd circuit shows that the inputs are given without any common mode unlike in the 1st circuit with Vc+Vd/2 and Vc-Vd/2. But the 2nd circuit would also require a minimum common mode for the circuit to operate.

yes it is only a sketch that I use to calculate the output range, but I know that a Vcm is needed!

Thanks for your patience and for your help.

 

[nitishn5]

Ok thanks!
So M5-M6 is a source follower to optimize the transfer of energy to load, and M7-M8 are the biasing transistor of the source follower stage.
It is correct?

Yes. It could also be for level-shifting.