For example Razavi, "Design of analog CMOS Integrated Circuits" 2nd ed. page 80, eq.(3.116). Or Carusone, David Johns Ken Martin "Analog Integrated Circuit Design" 2nd ed. page 126, eq.(3.20)
I'm attaching here a short derivation of the source resistance for the common gate stage.
Thank you for the literature information and your derivation.
However, one short comment seems to be in order: For further signal processing, the output (drain node) of the most right transistor must be connected to the 2nd stage. This results, of course, in a drastic change of the impedance effective at this node and - hence - of the input impedance at the source node.
Yes, what you're saying is correct, especially at high frequencies since the load from the next stage is mostly capacitive in most of the cases. The derivation in my previous post is for DC and low frequencies. At high frequencies, when the load capacitance starts to show up, the source impedance will converge to 1/gm and then at even higher frequencies there will be also a pole at the source.