# Differential amplifier with current source load

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#### Robotduck

##### Member level 2 In a Differential amplifier with current source load (using current mirror), why the node P ( source node of both input transistors ) is considered approximately ac grounded in most of the books when doing small signal analysis ? I do not understand this because the circuit is not symmetrical ...

#### rmanalo hello,

I assume you use Razavi's book in analog IC design? (hint from "node P")

Anyway, you can think of M1 and M2 as source followers since were concerned with the voltage at the source with respect to the gate. In this case it doesn't matter what the loads at the drain are. And since M1 and M2 are entirely the same and as long as the signals are differential then the node voltage Vp will always equal to the common mode voltage - gate-to-source voltage (Vin,cm - Vgs). • Robotduck

### Robotduck

points: 2

#### Robotduck

##### Member level 2 Yes, I use Razavi. Also for the common mode response ( in case of current mirror load), how can the voltages at node X and Y be equal ? Razavi explains this on page 149 with contradiction. I follow what he says but do you have a better explanation for this ?

#### rmanalo well if we assume that the transistor follows the square law. meaning id=k/2*(vgs-vth)^2*(1+lambda*vds)
vgs, id, and vds are the parameters concerned. given any two of these we can finde the other.
going back to your statement, M3 and M4 both carry equal currents, and equal vgs (since current mirror)
then therefore they have the same vds voltages or in this case equal voltages at node F and X. • Robotduck

### Robotduck

points: 2

#### Robotduck

##### Member level 2 In large signal analysis for Differential amplifier with current source load, how the output voltage is 0 when Vin1 is more negative than vin2 ?

Current through M1 and M3 is 0, So the current through M4 should also be zero, which means Vout= Vdd- 0*ro4= Vdd, but how come it is 0 ?

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#### rmanalo In large signal analysis for Differential amplifier with current source load, how the output voltage is 0 when Vin1 is more negative than vin2 ?

#### Robotduck

##### Member level 2 Current through M1 and M3 is 0, So the current through M4 should also be zero, which means Vout= Vdd- 0*ro4= Vdd, but how come it is 0 ?

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#### rmanalo Vout= Vdd- 0*ro4= Vdd
your statement is incorrect. m4 is off, and ideally the impedance between Vout and Vdd is infinity.
but in reality a very very small amount of current exist and the impedance between vout and vdd is very very large.
you can imagine this as a voltage divider where the resistance from vout to ground is the on resistances of M2 and M5 (both in deep triode)
you can see that Vout=Ron/(Ron+Rvdd-vout) which is approximately 0 since Rdd-vout is a very very large value.

• Robotduck

### Robotduck

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#### LvW In a Differential amplifier with current source load (using current mirror), why the node P ( source node of both input transistors ) is considered approximately ac grounded in most of the books when doing small signal analysis ? I do not understand this because the circuit is not symmetrical ...
It is the task of a diff. amplifier to amplify the difference between both inputs only. As a special case, one input can be zero (grounded).
Now we have the task to find the output voltage(s) for any arbritrary diff. input. For calculation purposes, we divide the whole process into two parts:

* Each of the two input voltages (V1, V2) can be split into (a) a common mode part Vc=(V1+V2)/2 and (b) a "full-differential" part Vdd=+-(V1-V2)/2.

* It is a simple task to find the corresponding gain expressions for the two cases. Finally, both parts of the output voltages (common and diff.) are superimposed again.

* Now, to your question: For the "full-diff." part we have V1=-V2, which means that the current increase in one transistor equals the current decrease in the other one. Hence, the potential at the point P remains constant. But this applies only to this case: V1=-V2.

* For the common mode voltage at the input (v1+V2)/2 the potential at P does NOT remain fixed. Therefore, we have a common mode gain which should be as small as possible (therefore we have a current source in the common leg instead of a large resistor).

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Further comment: Regarding the version with a current mirror load, the function can only be explained with a load (in practice: Another transistor) at the node Vout. The reason is simple: The current mirror forces the two currents to be equal. On the other hand, the input voltages will cause different currents (contradiction!). Therefore, the current difference (which is a measure of the amplification) is conveyed to the connected load.

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#### vivekroy

##### Full Member level 5 In a Differential amplifier with current source load (using current mirror), why the node P ( source node of both input transistors ) is considered approximately ac grounded in most of the books when doing small signal analysis ? I do not understand this because the circuit is not symmetrical ...
Look at the attached image.

Applying KCL at the tail node:
gm(delta_v-Vtail) + gm(-delta_v - Vtail) + (Vx-Vtail)/ro + (Vy-Vtail)/ro =0
If ro is large enough, then the last two terms can be ignored compared the first two terms. And then you will find v_tail = 0. #### sutapanaki Node P in current mirror loaded diff pair is not a virtual ground because the circuit is not symmetric as is the case in a fully differential and balanced diff pair. Here looking from the node P to the source of the left diff pair input transistor you see impedance in the order of 1/gm, while looking to the right you see a bigger impedance, especially at low frequencies. However, if you find the low frequency gain of the stage, it is approximately 2gm(rop||ron) and then equivalently it is like having that node P ac grounded. But electrically it wiggles when the amplifier works, hence it is not an ac ground even for small signals.

#### LvW ...... while looking to the right you see a bigger impedance, especially at low frequencies.hen the amplifier works, hence it is not an ac ground even for small
Sutapanaki.....please, can you explain WHY the input impedance looking into the right transistor is "bigger"?
Dont you think, this depends on the impedance connected to the gate of this transistor?

#### sutapanaki Sutapanaki.....please, can you explain WHY the input impedance looking into the right transistor is "bigger"?
Dont you think, this depends on the impedance connected to the gate of this transistor?
In DC and low frequencies the impedance or rather the resistance looking into the source of the right transistor is (1+rp/rn)/gm, where rp is ro of the PMOS transistor and rn is the ro of the NMOS transistor. For example, if the PMOS load is ideal current source with rp infinity, then resistance looking into the source of the right NMOS device is infinity too, because however you wiggle the source (with gate to ac ground), you won't be able to change the current of the ideal current source. In the other extreme - if rp<<rn, then you get the usual 1/gm looking into the source.

For higher frequencies, if there is impedance connected to the gate it will affect the impedance looking into the source when it starts coupling through the Cgs of the transistor. But I think this is not the case here with the initial question that was asked.

#### Robotduck

##### Member level 2 Differential amplifier with mismatch in Load resistance and ideal tail CS.

In the case of differential amplifier with ideal tail current source and mismatch in Rd, If we have a high frequency Commom mode noise, why does not it appear on the single ended output ? The single ended output should be disrupted. I understand that differential is smooth but how come single ended is also smooth if we have a ideal tail current source.

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#### FvM

##### Super Moderator
Staff member Pushing aside the unrealistic "infinite" load impedance considerations, you are right that the single ended differential amplifier becomes asymmetric with high load impedance, resulting e.g. in a poor CMRR.

You get acceptable symmetry with a load impedance << rout.

#### Robotduck

##### Member level 2 I did not follow. With mismatch in RD, and ideal tail current source, and high frequency common mode noise ,why does not we see the disturbance on the single ended output ?

#### sutapanaki I did not follow. With mismatch in RD, and ideal tail current source, and high frequency common mode noise ,why does not we see the disturbance on the single ended output ?
In the ideal case that you described even with mismatch in RD you should not expect to see CM variations in the outputs. The reason is that for common-mode, the amplifier is infinitely degenerated. It is the same as if you have a NMOS transistor with RD to the drain, an ideal current source in the source of the transistor and you apply some signal to the gate. Do you expect to see signal coming out at the drain?

#### LvW In DC and low frequencies the impedance or rather the resistance looking into the source of the right transistor is (1+rp/rn)/gm, where rp is ro of the PMOS transistor and rn is the ro of the NMOS transistor.
We are speaking about the input resistance at the source node, right? Identical to a common-gate configuration.
Can you tell me where the expression (1+rp/rn)/gm is coming from? Looks surprising to me.

#### sutapanaki In a common-gate configuration with gate at ac ground, looking into the source of the transistor with the drain loaded by some resistance which is at least with the order of magnitude as ro of the transistor, the resistance is as I showed it in my previous post. This source resistance is 1/gm if drain load resistance is small or if we disregard the effect of ro of the transistor (in other words consider it infinite). I could attach a derivation of the formula if you insist, but you can find it also in any book on analog transistor design.

BTW, in my previous post about the resistance looking right into the source of the diff pair I missed a factor of 2. The correct expression is (1+2rp/rn)/gm but this is only valid for diff pair loaded by a mirror. In the regular common gate, there is no factor of 2.

#### LvW In a common-gate configuration with gate at ac ground, looking into the source of the transistor with the drain loaded by some resistance which is at least with the order of magnitude as ro of the transistor, the resistance is as I showed it in my previous post. This source resistance is 1/gm if drain load resistance is small or if we disregard the effect of ro of the transistor (in other words consider it infinite). I could attach a derivation of the formula if you insist,but you can find it also in any book on analog transistor design.
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Do you speak about the diff. pair with a current source load?

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Do you speak about the diff. pair with a current source load?
Sutapanaki - I agree. I did not read your post#11 carefully enough. Now I have realized that you did not speak about the circuit in post#2 but about post#4 (active load). Sorry for the misinterpretation.

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