Differential Amp Problem

[hellotheworld]

Hello !
The image below is the simulation of my differential amplifier in dc analysis in pspice.
I struggled in finding the currents for \[ I_{d1}, I_{d2}, I_{d3} \]
I tried use \[ I_{d}=\frac{K_{n}}{2}(V_{GS}-V_{TN})^2 \] but I can't find the values as well as simulation does.

I also tried to find \[ V_{s1} \] by using \[ I_{d1}+I_{d2}=I_{d3} \] and then \[ I_{d}=\frac{K_{n}}{2}(V_{GS}-V_{TN})^2 \], but the final result does not match \[ V_{s1} \] in simulation.

In this simulation, assuming .model Mbreakn NMOS VTO=1 KP=100u LAMBDA=0 W=1u L=1u

 

[BradtheRad]

I think it would help if you get more current through the system. Mathematically its values add up, yet the mosfets are operating close to threshold of turn-on. Notice there is barely any voltage generated across R1 R2. As a result M1 M2 receive almost entire supply voltage. If you take output at their drain terminal, the output is very close to the supply rail.

It's hard to be sure how much M3 turns on? Its net Gate-to-source bias is -2.5 V, as a result of adding +1V applied directly, with negative voltage on its source terminal.

[Edited to add:]
Perhaps my figure for bias-gate-to-source voltage should be positive instead of negative. It's hard to evaluate because typically N-device is operated so that drain voltage is higher than gate voltage. However in this case drain and source are both less than gate voltage.

 

[BigBoss]

\[ V_{GS}=negative \]
How would you expect the currents flow ??You have to tie the Gates to Vdd by resistors (biasing resistors)