amir81
Member level 2
hi all
i wrote a project in vhdl. when i use fpga express it does not infer any latch or ff but leonardo says "signal is not always assigned. Storage may be needed.." . i reread the code to become sure thar signals always assigned in all cases and if-thens but they are always assigned. does anyone know what the problem is?
thanks
amir
i wrote a project in vhdl. when i use fpga express it does not infer any latch or ff but leonardo says "signal is not always assigned. Storage may be needed.." . i reread the code to become sure thar signals always assigned in all cases and if-thens but they are always assigned. does anyone know what the problem is?
thanks
amir