batmanbeginz
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Hi all,
I am new to analog design. I have created an op-amp schematic and tried to get open loop gain by 2 ways:
(Simulation uses cadence virtuoso)
1) Transient analysis: applied a ramp pulse of 0->VDD to +ve input [with a dc value of VDD/2] and kept -ve input to Vdd/2, then plotted Vout vs V+ and took its derivative, this gave me 1300
2) DC analysis: applied a volt of 0->VDD at +ve volt and kept -ve input to VDD/2. Processed Vout as in step 1 and got ~ 50
I cannot believe what makes the 2 gains so different and which is correct ? Voltage supply is from 0->VDD.
Can someone help in this regard ?
Thanks a lot
I am new to analog design. I have created an op-amp schematic and tried to get open loop gain by 2 ways:
(Simulation uses cadence virtuoso)
1) Transient analysis: applied a ramp pulse of 0->VDD to +ve input [with a dc value of VDD/2] and kept -ve input to Vdd/2, then plotted Vout vs V+ and took its derivative, this gave me 1300
2) DC analysis: applied a volt of 0->VDD at +ve volt and kept -ve input to VDD/2. Processed Vout as in step 1 and got ~ 50
I cannot believe what makes the 2 gains so different and which is correct ? Voltage supply is from 0->VDD.
Can someone help in this regard ?
Thanks a lot