Different libraries being used in Synthesis

[limitless_21]

Hi All,

Can anybody let me know what is the difference between DEF, LEF and Captable files which are being used in synthesis with their full forms.
I am using RTL compiler for Synthesis.

Also what id the major difference between , wireload synthesis, PLE flow and Physical synthesis if we do it in RC.

Thanks
Limitless

 

[rca]

DEF: design exchange file/format, could contains, netlist, routing, via, nets...
LEF: Library Exchange File, define physically the element (std cell-memories-pads...)
Captable: is precompute capacitance table to estimate the delay due to nets.

wireload model: basic estimation of the network delay into the path delay.
PLE flow: the network delay is calculate based on the technology LEF information's and the captable.
Physical synthesis: the floorplan is provided via a DEF file, and RC could improve his network delay estimation, because he knows where the std cell could be placed, and where are the macro's element.

 

[kenambo]

DEF: design exchange file/format, could contains, netlist, routing, via, nets...
LEF: Library Exchange File, define physically the element (std cell-memories-pads...)
Captable: is precompute capacitance table to estimate the delay due to nets.

wireload model: basic estimation of the network delay into the path delay.
PLE flow: the network delay is calculate based on the technology LEF information's and the captable.
Physical synthesis: the floorplan is provided via a DEF file, and RC could improve his network delay estimation, because he knows where the std cell could be placed, and where are the macro's element.

Hi

is it possible to measure timing in RTL compiler(cadence)...
thanks

 

[rca]

what do you mean measure timing?
with RC, you could only report the timing path, with information of the slew/cap estimated by the tool.
we can not measure like analog designer do with timing grap.

 

[mr_vasanth]

The result (timing and placement) of physical synthesis, will be more closer to the final layout result as we take the placement and cell's physical attribute information from the layout team in advance through DEF file and use it during DC synthesis. Physical synthesis is more advantageous as we tackle the placement and timing related issues at synthesis stage itself instead of tackling at the layout stage.