verilog+pli vera e systemc system-verilog
easy easy hard hard easy
event base cycle base cycle base cycle base event base
co-simulation co-simulation co-simulation co-simulation co-simulation
need pli to can control can control can control may control <--(control memory)
no class class class class class
slow quick quick quick slow
no assert assert assert no assert
IEEE synopsys cadence IEEE synopsys/Cadence
random limit random random random random