Difference in updating output value of an FF and a latch in verilog

[biju4u90]

Of course this is a very basic question in verilog. But I am confused how!!
Consider the two verilog codes given.

Code 1:
module test1(A,B,C,D);
input A,B,C;
output reg D;
always @(posedge A)
begin
if (B==0)
D=C;
end
endmodule

Code 2:
module test2(A,B,C,D);
input A,B,C;
output reg D;
always @(posedge A)
begin
if (B==1)
D=0;
else
D=C;
end
endmodule

For both the cases, I give the same test bench,
initial begin
A = 0;B = 0;C = 0;
#100;
B=1; C=1; A=1;
end

It is seen that the output D takes the new value of C at positive edge of A and becomes '1' in the first case whereas, D takes the old value of C at positive edge of A and becomes '0' in the second case. Of course I see the difference in the RTL schematic generated, the second case generates an edge triggered one. But why the second case assigns the previous value of C while the first case assigns the updated value of C at the posedge of A?

 

[sharath666]

The first case infers a latch and the second infers a flop(with B as reset to the flop). The behaviour is correct. The flop always takes the old value and assigns it to it's output.

 

[ads-ee]

It is seen that the output D takes the new value of C at positive edge of A and becomes '1' in the first case whereas.

Had a hard time believing this statement so I ran a simulation on the code and as I thought the output of D for the first case is X as D was not defined at the beginning of the simulation and C is set high before the rising edge of A (blocking statements are order dependent). It also does not generate a latch in synthesis as the always block is edge sensitive so the implementation will have a FlipFlop.

D takes the old value of C at positive edge of A and becomes '0' in the second case. Of course I see the difference in the RTL schematic generated, the second case generates an edge triggered one. But why the second case assigns the previous value of C while the first case assigns the updated value of C at the posedge of A?

I really don't understand your point here, the two codes are functionally different so therefore they will have different RTL schematics and will also behave differently. test1 has an active low enable and test2 has an active high reset.

BTW you better read up on when to use blocking (=) v.s. non-blocking (<=) assignments in Verilog.

 

[biju4u90]

Sorry. That was my mistake.