#### biju4u90

##### Full Member level 3

Consider the two verilog codes given.

**Code 1:**

module test1(A,B,C,D);

input A,B,C;

output reg D;

always @(posedge A)

begin

if (B==0)

D=C;

end

endmodule

**Code 2:**

module test2(A,B,C,D);

input A,B,C;

output reg D;

always @(posedge A)

begin

if (B==1)

D=0;

else

D=C;

end

endmodule

For both the cases, I give the same test bench,

initial begin

A = 0;B = 0;C = 0;

#100;

B=1; C=1; A=1;

end

It is seen that the output D takes the new value of C at positive edge of A and becomes '1' in the first case whereas, D takes the old value of C at positive edge of A and becomes '0' in the second case. Of course I see the difference in the RTL schematic generated, the second case generates an edge triggered one. But why the second case assigns the previous value of C while the first case assigns the updated value of C at the posedge of A?