difference between technical and RTL schematic in ISE 10.1

[gck]

rtl schematic and technology schematic

I am using ISE 10.1. I have written following code for dff.
library ieee;
use ieee.std_logic_1164.all;

entity dff is

port (
clk : in std_logic;
rst_a : in std_logic;
din : in std_logic;
qoutb : out std_logic;
qout : out std_logic);

end dff;

architecture dff_arc of dff is
signal qout_s : std_logic;
begin -- dff_arc

dff_p: process (clk, rst_a)
begin -- process dff_p
if rst_a = '1' then -- asynchronous reset (active low)
qout_s <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
qout_s <= din;

end if;
end process dff_p;

qout <= qout_s;
qoutb <= not(qout_s);

end dff_arc;

In RTL view, it showing one dff and qout and qoutb drawn from qout_s with difference of not gate.

In tec view, it is using two dff for two outputs.

 

[FvM]

difference between rtl and other logic families

As a first point, you should consider that the RTL to technology mapping always causes structural differences, for various reasons. If you think about, you most likely find the reasons in effect in your simple example.

Of course, the fitter result depends on the utilized logic family, but I guess, the registers don't have inverted outputs in your case. That would be already a plausible reason. For internal registers, a succeeding logic element causing additional tco delay would be the alternative, for an output register, this option didn't exist at all.

 

[vipinlal]

hope this helps:
https://vhdlguru.blogspot.com/2010/03/xilinx-ise-help-using-rtl-and.html