what are diff btw synthesis and design
Uhm, I think I did. It's not the 1st time I did timing simulation, just use Xilinx ISE 10.1 to generate primetime ( gate level ) netlist and back-annotate SDF file before doing simulation in ModelSIM, right? Did I miss sth?
Uhm, now, the design, which is passed in timing simulation, does a mess on real board running. It is an image processing application with some memory manipulations. After making sure that memory is initialized, I pressed START. But all the things I got is a totally cleared memory which actually must be filtered image. Do you think what causes this?
PS: thanks for your suggestion.