Difference between Synthesis timing report & Simulation

[FINALFANTASYFAN]

difference between simulation and synthesis

Xilinx ISE 10.1 reports that my design has T-clock-to-setup=15.598ns and the longest ( critical ) path takes about 14ns. But the timing simulation in ModelSIM goes wrong, nothing changes their values when I run on clock of 50Mhz( period= 20ns). If clock is 20Mhz, everything is OK, the outputs are great.

So the synthesis timing report is too unreliable, isn't it? Because the "guard period" is about 5ns to the real clock cycle ( 20ns )

PS: I downloaded this design into board but it didn't work at 50MHz

 

[dcreddy1980]

what is diff btw synthesis and design

Did you properly backannoate the SDF file to the gat level netlist whicle running simulation

 

[FINALFANTASYFAN]

what are diff btw synthesis and design

Uhm, I think I did. It's not the 1st time I did timing simulation, just use Xilinx ISE 10.1 to generate primetime ( gate level ) netlist and back-annotate SDF file before doing simulation in ModelSIM, right? Did I miss sth?


Uhm, now, the design, which is passed in timing simulation, does a mess on real board running. It is an image processing application with some memory manipulations. After making sure that memory is initialized, I pressed START. But all the things I got is a totally cleared memory which actually must be filtered image. Do you think what causes this?



PS: thanks for your suggestion.