Difference between synthesis and translate

[hithesh123]

In Xilinx ISE, what is the difference between Synthesis and translate.
Synthesis is where your code is converted to gate level netlist. This is basically xilinx primitives. Synthesis is technology independent?
Translate just converts technology independent file (.ngc file/EDIF file) to technology dependent file (.ngd file)(particular device/package)?

What exactly does technology independent mean? Does it mean independent of any particular fpga, like spartan or vertex?

 

[mrflibble]

Technology independent means that the result should be the same, regardless of the target device being for example LUT4 (spartan3) or LUT6 (spartan6).

 

[permute]

translate takes the synthesis results, the UCF file, and other existing cores (in netlist form) and merges them together.

MAP is what traditionally selects elements on the FPGA.

PAR really only does routing, but previously also did placement.

- - - Updated - - -

translate takes the synthesis results, the UCF file, and other existing cores (in netlist form) and merges them together.

MAP is what traditionally selects elements on the FPGA.

PAR really only does routing, but previously also did placement.

 

[mrflibble]

I was under the impression that PAR still did do placement? Maybe it's time for me to pay more attention during the next map + par run.

 

[hithesh123]

Can you elaborate a little on - synthesis uses unisim library components and translate uses simprim library components.
I thought simprim was for simulation.

I was under the impression that PAR still did do placement? Maybe it's time for me to pay more attention during the next map + par run.

Me too!

 

[jimwu88]

Starting Virtex5, map -timing (timing driven map/placement) is the only option for "Map" phase, which does both map and placement. "Par" may move things around for better routing, but it's very minor movement. Its main job is routing.

I was under the impression that PAR still did do placement? Maybe it's time for me to pay more attention during the next map + par run.

 

[TuAtAu]

synthesis have HARDWARE limitation involved in synthesis(translation or so called converting from VHDL).

translate is free from hardware limitation (such as GATES limit, slice limit, BRAM limit etc from ur FPGA/board)

Hopes helps